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S29PL-J65BFW012 Datasheet(PDF) 9 Page - SPANSION |
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S29PL-J65BFW012 Datasheet(HTML) 9 Page - SPANSION |
9 / 96 page September 22, 2006 S29PL-J_00_A9 S29PL-J 7 Da ta Sh e e t (Adv a n ce In f o r m ation) 1. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: 1.1 Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Bank PL127J Sectors PL064J Sectors PL032J Sectors A 16 Mbit (4 Kw x 8 and 32 Kw x 31) 8 Mbit (4 Kw x 8 and 32 Kw x 15) 4 Mbit (4 Kw x 8 and 32 Kw x 7) B 48 Mbit (32 Kw x 96) 24 Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24) C 48 Mbit (32 Kw x 96) 24 Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24) D 16 Mbit (4 Kw x 8 and 32 Kw x 31) 8 Mbit (4 Kw x 8 and 32 Kw x 15) 4 Mbit (4 Kw x 8 and 32 Kw x 7) Bank PL129J Sectors CE# Control 1A 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE1# 1B 48 Mbit (32 Kw x 96) CE1# 2A 48 Mbit (32 Kw x 96) CE2# 2B 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE2# |
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