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S29PL127N65FFWW02 Datasheet(PDF) 3 Page - SPANSION |
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S29PL127N65FFWW02 Datasheet(HTML) 3 Page - SPANSION |
3 / 85 page Publication Number S29PL-N_00 Revision A Amendment 4 Issue Date November 23, 2005 General Description The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm MirrorbitTM Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to op- erate without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and CE2#) that allow each half of the memory space to be controlled separately. Distinctive Characteristics Architectural Advantages 32-Word Write Buffer Dual Chip Enable Inputs (only for S29PL129N) — Two CE# inputs control selection of each half of the memory space Single Power Supply Operation — Full Voltage range of 2.7 – 3.6 V read, erase, and program operations for battery-powered applications — Voltage range of 2.7 – 3.1 V valid for PL-N MCP products Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations 4-Bank Sector Architecture with Top and Bottom Boot Blocks 256-Word Secured Silicon Sector Region — Up to 128 factory-locked words — Up to 128 customer-lockable words Manufactured on 0.11 µm Process Technology Data Retention of 20 years Typical Cycling Endurance of 100,000 Cycles per Sector Typical Hardware Features WP#/ACC (Write Protect/Acceleration) Input —At VIL, hardware level protection for the first and last two 32 Kword sectors. —At VIH, allows the use of DYB/PPB sector protection —At VHH, provides accelerated programming in a factory setting Dual Boot and No Boot Options Low VCC Write Inhibit Security Features Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level Password Sector Protection — A sophisticated sector protection method locks combinations of individual sectors to prevent program or erase operations within that sector using a user defined 64-bit password Performance Characteristics Note: : Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 10,000 cycles; checkerboard data pattern. S29PL-N MirrorBit™ Flash Family S29PL256N, S29PL127N, S29PL129N, 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory Data Sheet PRELIMINARY Read Access Times (@ 30 pF, Industrial Temp.) Random Access Time, ns (tACC)65 70 80 Page Access Time, ns (tPACC)25 30 30 Max CE# Access Time, ns (tCE)65 70 80 Max OE# Access Time, ns (tOE)25 30 30 Current Consumption (typical values) 8-Word Page Read 6 mA Simultaneous Read/Write 65 mA Program/Erase 25 mA Standby 20 µA Typical Program & Erase Times (typical values) (See Note) Typical Word 40 µs Typical Effective Word (32 words in buffer) 9.4 µs Accelerated Write Buffer Program 6 µs Typical Sector Erase Time (32-Kword Sector) 300 ms Typical Sector Erase Time (128-Kword Sector) 1.6 s Package Options S29PL-N VBH064 8.0 x 11.6 mm, 64-ball VBH084 8.0 x 11.6 mm, 84-ball LAA064 11 x 13 mm, 64-ball Fortified BGA 256 129 127 |
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