for Audio Applications

8

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The following terminology is commonly used to

(Figure 3) and the

table for additional information.

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses, start and stop conditions.

Slave Devices: Slave devices send and receive data

at the master’s request.

Bus Idle or Not Busy: Time between stop and start

conditions when both SDA and SCL are inactive and in

their logic-high states.

Start Condition: A start condition is generated by the

master to initiate a new data transfer with a slave.

Transitioning SDA from high to low while SCL remains

high generates a start condition.

Stop Condition: A stop condition is generated by the

master to end a data transfer with a slave. Transitioning

SDA from low to high while SCL remains high gener-

ates a stop condition.

Repeated Start Condition: The master can use a

repeated start condition at the end of one data transfer

to indicate that it will immediately initiate a new data

transfer following the current one. Repeated starts are

commonly used during read operations to identify a

specific memory address to begin a data transfer. A

repeated start condition is issued identically to a nor-

mal start condition.

Bit Write: Transitions of SDA must occur during the low

state of SCL. The data on SDA must remain valid and

unchanged during the entire high pulse of SCL plus the

setup and hold time requirements. Data is shifted into

the device during the rising edge of the SCL.

Bit Read: At the end of a write operation, the master

must release the SDA bus line for the proper amount of

setup time before the next rising edge of SCL during a

bit read. The device shifts out each bit of data on SDA at

the falling edge of the previous SCL pulse and the data

bit is valid at the rising edge of the current SCL pulse.

Remember that the master generates all SCL clock

pulses including when it is reading bits from the slave.

Acknowledgement (ACK and NACK): An Acknowledge-

ment (ACK) or Not Acknowledge (NACK) is always the

9th bit transmitted during a byte transfer. The device

receiving data (the master during a read or the slave dur-

ing a write operation) performs an ACK by transmitting a

zero during the 9th bit. A device performs a NACK by

transmitting a one (done by releasing SDA) during the 9th

bit. Timing (Figure 3) for the ACK and NACK is identical to

all other bit writes. An ACK is the acknowledgment that

the device is properly receiving data. A NACK is used to

terminate a read sequence or as an indication that the

device is not receiving data.

Byte Write: A byte write consists of 8 bits of informa-

tion transferred from the master to the slave (most sig-

nificant bit first) plus a 1-bit acknowledgement from the

slave to the master. The 8 bits transmitted by the mas-

ter are done according to the bit write definition and the

acknowledgement is read using the bit read definition.

SDA

SCL

REPEATED

START

STOP

START