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S29NS-J Datasheet(PDF) 3 Page - SPANSION |
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S29NS-J Datasheet(HTML) 3 Page - SPANSION |
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3 / 85 page  March 22, 2006 S29NS-J_01_A10 S29NS-J iii Data Sheet Table Of Contents Notice On Data Sheet Designations . . . . . . . . . . . ii Advance Information .......................................................................................ii Preliminary ..........................................................................................................ii Combination .......................................................................................................ii Full Production (No Designation on Document) ...................................ii Simultaneous Read/Write Operations with Zero Latency ......................2 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram of Simultaneous Operation Circuit 5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12 Valid Combinations .............................................................................................13 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 14 Table 1. Device Bus Operations ........................................... 14 Requirements for Asynchronous Read Operation (Non-Burst) .......... 14 Requirements for Synchronous (Burst) Read Operation ....................... 14 Continuous Burst .............................................................................................15 8-, 16-, and 32-Word Linear Burst with Wrap Around .......................15 Table 2. Burst Address Groups ............................................ 16 8-, 16-, and 32-Word Linear Burst without Wrap Around ................ 16 Programmable Wait State ................................................................................ 16 Handshaking Feature ......................................................................................17 Simultaneous Read/Write Operations with Zero Latency .....................17 Writing Commands/Command Sequences ..................................................17 Accelerated Program Operation ................................................................17 Autoselect Functions ......................................................................................17 Standby Mode ........................................................................................................17 Automatic Sleep Mode ...................................................................................... 18 RESET#: Hardware Reset Input ..................................................................... 18 VCC Power-up and Power-down Sequencing ........................................ 18 Output Disable Mode ........................................................................................ 18 Hardware Data Protection .............................................................................. 18 WP# Boot Sector Protection ......................................................................... 19 Low VCC Write Inhibit ................................................................................ 19 Write Pulse “Glitch” Protection ................................................................ 19 Logical Inhibit ................................................................................................... 19 Common Flash Memory Interface (CFI) . . . . . . 20 Table 3. CFI Query Identification String ................................ 20 Table 4. System Interface String ......................................... 20 Table 5. Device Geometry Definition .................................... 21 Table 6. Primary Vendor-Specific Extended Query ................. 21 Table 7. Sector Address Table, S29NS128J ........................... 23 Table 8. Sector Address Table, S29NS064J ........................... 27 Table 9. Sector Address Table, S29NS032J ........................... 31 Table 10. Sector Address Table, S29NS016J ......................... 32 Command Definitions ........................................................................................33 Reading Array Data ............................................................................................33 Set Configuration Register Command Sequence ......................................34 Table 11. Burst Modes ....................................................... 34 Handshaking Feature .....................................................................................34 Table 12. Wait States for Handshaking ................................. 35 Sector Lock/Unlock Command Sequence ...................................................35 Reset Command ..................................................................................................35 Autoselect Command Sequence ....................................................................36 Table 13. Autoselect Device ID ............................................ 36 Program Command Sequence ........................................................................36 Unlock Bypass Command Sequence .........................................................37 Figure 1. Program Operation ............................................... 38 Chip Erase Command Sequence ................................................................... 38 Sector Erase Command Sequence ................................................................ 39 Accelerated Sector Group Erase .............................................................. 39 Table 14. Accelerated Sector Erase Groups, S29NS128J ......... 40 Table 15. Accelerated Sector Erase Groups, S29NS064J ......... 40 Table 16. Accelerated Sector Erase Groups, S29NS032J ......... 41 Table 17. Accelerated Sector Erase Groups, S29NS016J ......... 41 Erase Suspend/Erase Resume Commands .................................................. 42 Figure 2. Erase Operation ................................................... 43 Table 18. Command Definitions .......................................... 44 DQ7: Data# Polling ............................................................................................ 45 Figure 3. Data# Polling Algorithm ........................................ 46 RDY: Ready ...........................................................................................................47 DQ6: Toggle Bit I ............................................................................................... 47 DQ2: Toggle Bit II .............................................................................................. 47 Figure 4. Toggle Bit Algorithm ............................................. 48 Table 19. DQ6 and DQ2 Indications ..................................... 49 Reading Toggle Bits DQ6/DQ2 .....................................................................49 DQ5: Exceeded Timing Limits ........................................................................49 DQ3: Sector Erase Timer ................................................................................50 Table 20. Write Operation Status ......................................... 50 Figure 5. Maximum Negative Overshoot Waveform ................ 51 Figure 6. Maximum Positive Overshoot Waveform.................. 51 Operating Ranges ................................................................................................ 51 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 7. Test Setup .......................................................... 53 Table 21. Test Specifications ............................................... 53 Key to Switching Waveforms . . . . . . . . . . . . . . . 53 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 53 Figure 8. Input Waveforms and Measurement Levels.............. 53 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54 VCC Power-up .....................................................................................................54 Figure 9. VCC Power-up Diagram.......................................... 54 CLK Characterization ....................................................................................... 55 Figure 10. CLK Characterization........................................... 55 Synchronous/Burst Read .................................................................................. 56 Figure 11. Burst Mode Read (66 and 54 MHz)........................ 56 Figure 12. Burst Mode Read (40 MHz) .................................. 57 Asynchronous Read ...........................................................................................58 Figure 13. Asynchronous Mode Read .................................... 58 Figure 14. Reset Timings .................................................... 59 Erase/Program Operations ..............................................................................60 Figure 15. Program Operation Timings ................................. 61 Figure 16. Chip/Sector Erase Operations............................... 62 Figure 17. Accelerated Unlock Bypass Programming Timing..... 63 Figure 18. Data# Polling Timings (During Embedded Algorithm) ... 64 Figure 19. Toggle Bit Timings (During Embedded Algorithm) ... 64 Figure 20. 8-, 16-, and 32-Word Linear Burst Address Wrap Around 65 Figure 21. Latency with Boundary Crossing ........................... 65 Figure 22. Initial Access at 3Eh with Address Boundary Latency 66 Figure 23. Example of Extended Valid Address Reducing Wait State Usage .............................................................................. 66 Figure 24. Back-to-Back Read/Write Cycle Timings ................ 67 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 68 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 69 S29NS128J ..............................................................................................................69 VDC048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 10 x |
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