6

S75WS-N Based MCPs

S75WS-N_02_A2 October 6, 2005

Prel imi n ary

4

MCP Block Diagram

Notes:

1. MRS is only present in RAM Type 4.

2. CE#f1, CE#f2, and CE#f3 are the chip enable pins for the first, second and third Flash devices, respectively.

Figure 4.1 MCP Block Diagram 1

A0-A22

A0-A22

A23

A23

RDY

RDY

DQ0-DQ15

CLK

CLK

AVD#

AVD#

F1-CE#

CE#

OE#

OE#

F-RST#

RESET#

VSS

VSS

F-ACC

ACC

F1-WP#

WP#

F-WE#

WE#

VCC

F-VCC

VCCQ

F-VCCQ

A0-A22

WAIT#

CLK

AVD#

R-CE#

CE#

OE#

R-LB#

LB#

R-UB#

UB#

WE#

R-MRS#

MRS#

VSS

VCC

R-VCC

VCCQ

R-VCCQ

A0-A22

A23

RDY

CLK

AVD#

F2-CE#

CE#

OE#

RESET#

ACC

FD-WP#

WP#

WE#

VSS

VCC

VCCQ

A0-A22

A23

RDY

CLK

AVD#

F3-CE#

CE#

OE#

RESET#

ACC

WP#

WE#

VSS

VCC

VCCQ

DQ0-DQ15

DQ0-DQ15

DQ0-DQ15

DQ0-DQ15

WS256N

Flash

Memory

128Mb

Memory

WS256N

Flash

Memory

WS256N

Flash

Memory

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