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SN74LVC137A Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC137A Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page www.ti.com FEATURES 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 A B C G2A G2B G1 Y7 GND VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 D, DB, OR PW PACKAGE (TOP VIEW) DESCRIPTION SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C • Inputs Accept Voltages to 5.5 V • Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages This 3-line to 8-line decoder/demultiplexer, with latches on three address inputs, is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC137A is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. When the latch-enable (G2A) input is low, the SN74LVC137A acts as a decoder/demultiplexer. When G2A transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further address changes are ignored, provided G2A remains high. The output-enable (G1 and G2B) inputs control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2B is high. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN74LVC137A is characterized for operation from –40 °C to 85°C. FUNCTION TABLE INPUTS OUTPUTS LATCH OUTPUT SELECT ENABLE ENABLE G2A G1 G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X L X X X X H H H H H H H H L H L L L L L H H H H H H H L H L L L H H L H H H H H H L H L L H L H H L H H H H H L H L L H H H H H L H H H H L H L H L L H H H H L H H H L H L H L H H H H H H L H H L H L H H L H H H H H H L H L H L H H H H H H H H H H L H H L X X X Outputs corresponding to stored address = L; all other outputs = H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. PRODUCT PREVIEW information concerns products in the forma- Copyright © 1994–2005, Texas Instruments Incorporated tive or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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