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QR0001 Datasheet(PDF) 28 Page - National Semiconductor (TI) |
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QR0001 Datasheet(HTML) 28 Page - National Semiconductor (TI) |
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28 / 40 page  110 Board Considerations (Continued) 286 ns The QuickRing UpPort needs 236 ns of this bit width (including transitions) to successfully sample the val- ue for each sub-symbol This allows for a total skew budget of 05 ns The interconnect between DnPort and UpPort should be limited to 350 ps This provides 150 ps skew mar- gin The 350 ps can be divided between PCB traces con- nectors headers cables and all other media used in the signal path The skew within a pair needs to be controlled because of the EMI considerations The simultaneous and opposite transitions on paths within a pair create equal and opposing electromagnetic fields These EMF the source of EMI serve to cancel each other thereby reducing EMI The skew within a pair should be controlled so that the single ended EMF remain temporally and spatially relevant for the cancel- ing affect The length of node interconnects is not critical to the opera- tion of QuickRing until it degrades signal integrity Nodes in a ring can have different length interconnects The maxi- mum length of the interconnect depends on two qualities of the interconnect transition time degradation and amplitude antenuation Any extension in transition time due to the high frequency filter affect of the interconnect takes away from the skew budget The trade offs between the skew and tran- sition time degradation must be balanced to allow for the correct amount of sample time for the UpPort The signal attenuation affects the differential signal ampli- tude at the receiver input The receiver requires a differen- tial voltage of at least 100 mV to guarantee a state The receiver actually is more sensitive than that under typical operating conditions but due to power supply and tempera- ture variations and test limitations this is the data sheet specification As long as the differential voltage is guaran- teed to be at least 150 mV and all the skew budget specifi- cations are met the receiver will operate correctly with ade- quate noise margin 120 Power and Decoupling Issues 121 Power Issues The QR0001 device internally has Four distinct Power re- gions These regions are labeled (Refer to Figure 123 ) 1 Logic Power Pins (VCC 451213 GND 31518192829) 2 Client Receive Port Output Power Pins (VCC 67891011 GND 2021222324252627) 3 LVDS Power Pins (VCC 13 GND 124567810111213141617) 4 PLL and Delay Element Power Pins (VCC 2 GND 9) It is currently recommended that the PC Board have sepa- rate GND and VCC planes Also Power Region 2 should have some additional isolation from the power plane Com- plete isolation is not required The isolation aids in limiting the Receive Port current spikes to the remaining plane Re- fer to Figure 121 122 Decoupling Issues lt is currently recommended that capacitors be placed local- ly on all four corners of the device to provide an even filter- ing Capacitors should also be placed close to power region 2 to provide additional noise filtering Refer to Figure 121 Two capacitors should be placed in parallel to get high and low frequency filtering along each side However each ca- pacitor should have a via directiy to the VCC and Ground planes For power region 4 (PLL and Delay Element Power Pin) two decoupling capacitors should be placed as close to the pins as possible (between VCC2 and GND9) A trace from the pin directly to the capacitors is recommended and separate vias to ground plane for each capacitor Refer to Figure 121 TLF11928 – 28 FIGURE 121 QR0001 Power Region Isolation 28 |
Similar Part No. - QR0001 |
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Similar Description - QR0001 |
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