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S29CD032G0MQAM102 Datasheet(PDF) 10 Page - SPANSION |
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S29CD032G0MQAM102 Datasheet(HTML) 10 Page - SPANSION |
10 / 87 page 8S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Prel imi n ary Figures Figure 1. Asynchronous Read Operation ............................................................................................................................................................................ 27 Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation ...........................................................................29 Figure 3. Initial Burst Delay Control.....................................................................................................................................................................................30 Figure 4. Program Operation .................................................................................................................................................................................................. 45 Figure 5. Erase Operation ........................................................................................................................................................................................................48 Figure 6. Data# Polling Algorithm.......................................................................................................................................................................................... 57 Figure 7. Toggle Bit Algorithm................................................................................................................................................................................................60 Figure 8. Maximum Negative Overshoot Waveform ......................................................................................................................................................62 Figure 9. Maximum Positive Overshoot Waveform.........................................................................................................................................................62 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)................................................................................................65 Figure 11. Typical ICC1 vs. Frequency ......................................................................................................................................................................................65 Figure 12. Test Setup....................................................................................................................................................................................................................66 Figure 13. Input Waveforms and Measurement Levels .....................................................................................................................................................66 Figure 14. VCC and VIO Power-up Diagram..........................................................................................................................................................................67 Figure 15. Conventional Read Operations Timings............................................................................................................................................................68 Figure 16. Burst Mode Read.......................................................................................................................................................................................................70 Figure 17. Asynchronous Command Write Timing............................................................................................................................................................70 Figure 18. Synchronous Command Write/Read Timing..................................................................................................................................................... 71 Figure 19. RESET# Timings......................................................................................................................................................................................................... 72 Figure 20. WP# Timing................................................................................................................................................................................................................ 72 Figure 21. Chip/Sector Erase Operation Timings................................................................................................................................................................ 74 Figure 22. Back-to-Back Cycle Timings .................................................................................................................................................................................. 74 Figure 23. Data# Polling Timings (During Embedded Algorithms) ................................................................................................................................ 75 Figure 24. Toggle Bit Timings (During Embedded Algorithms)....................................................................................................................................... 75 Figure 25. DQ2 vs. DQ6 for Erase/Erase Suspend Operations...................................................................................................................................... 76 Figure 26. Synchronous Data Polling Timing/Toggle Bit Timings.................................................................................................................................... 76 Figure 27. Sector Protect/Unprotect Timing Diagram ...................................................................................................................................................... 77 Figure 28. Alternate CE# Controlled Write Operation Timings...................................................................................................................................78 |
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