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S71WS256NB0BAWTP0 Datasheet(PDF) 7 Page - SPANSION |
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S71WS256NB0BAWTP0 Datasheet(HTML) 7 Page - SPANSION |
7 / 13 page July 19, 2006 S71WS-N_00_A6 S71WS-N 5 Da ta Sh e e t (Adv a n ce In f o r m ation) 4. MCP Block Diagram Notes: 1. R-CRE is only present in CellularRAM-compatible pSRAM. 2. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash. 3. Only needed for S71WS512N. 4. For the 128M pSRAM devices, there are 23 shared addresses. 5. Connection Diagrams/Physical Dimensions This section contains the I/O designations and package specifications for the S71WS-N. 5.1 Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. VID VCC RDY pSRAM Flash 1 DQ15 to DQ0 Flash-only Address Shared Address F1-CE# ACC R-UB# R-CE2 R-CRE R-VCC VCC VCCQ F-VCC 22 CLK CLK WP# OE# WE# F-RST# AVD# CE# ACC WP# OE# WE# RESET# AVD# RDY VSS VSSQ DQ15 to DQ0 16 I/O15 to I/O0 16 R-CE1# CE# WE# OE# UB# R-LB# LB# 22 F2-CE# CLK AVD# Flash 2 WAIT# CRE# (Note 1) (Note 2) (Note 2) (Note 4) |
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