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S71NS256NA0BJWRN3 Datasheet(PDF) 5 Page - SPANSION

Part # S71NS256NA0BJWRN3
Description  MirrorBit 1.8 Volt-only Simultaneous Read/Write, Burst-mode Multiplexed Flash Memory
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S71NS256NA0BJWRN3 Datasheet(HTML) 5 Page - SPANSION

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October 10, 2006 S71NS-N_00_A3
S71NS-N MCP Products
3
Advance
Information
2
Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Description
Flash
RAM
AMAX – A16
Address inputs
XX
ADQ15 – ADQ0
Multiplexed Address/Data
X
X
OE#
Output Enable input. Asynchronous relative to CLK for the Burst mode.
X
X
WE#
Write Enable input.
X
X
VSS
Ground
XX
NC
No Connect; not connected internally
X
X
RDY
Ready output. Indicates the status of the Burst read. The WAIT# pin of the
pSRAM is tied to RDY.
XX
CLK
Clock input. In burst mode, after the initial word is output, subsequent
active edges of CLK increment the internal address counter. Should be at
VIL or VIH while in asynchronous mode
XX
AVD#
Address Valid input. Indicates to device that the valid address is present
on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode,
causes starting address to be latched.
High = device ignores address inputs
XX
F-RST#
Hardware reset input. Low = device resets and returns to reading array
data
X
F-WP#
Hardware write protect input. At VIL, disables program and erase functions
in the four outermost sectors. Should be at VIH for all other conditions.
X
F-ACC
Accelerated input. At VHH, accelerates programming; automatically places
device in unlock bypass mode. At VIL, disables all program and erase
functions. Should be at VIH for all other conditions.
X
R-CE1#
Chip-enable input for pSRAM.
X
F-CE#
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
X
R-CRE
Control Register Enable (pSRAM).
X
F-VCC
Flash 1.8 Volt-only single power supply.
X
R-VCC
pSRAM Power Supply.
X
R-UB#
Upper Byte Control (pSRAM).
X
R-LB#
Lower Byte Control (pSRAM)
X
DNU
Do Not Use


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