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S29CD016G0JFFM110 Datasheet(PDF) 4 Page - SPANSION |
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S29CD016G0JFFM110 Datasheet(HTML) 4 Page - SPANSION |
4 / 87 page 2S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Prel imi n ary General Description The S29CD-G Flash Family is a burst mode, Dual Boot, Simultaneous Read/Write family of Flash Memory with VersatileI/O™ manufactured on 170 nm Process Technology. The S29CD032G is a 32 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be configured for 1,048,576 double words. The S29CD016G is a 16 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be configured for 524,288 double words. To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Additional control inputs are required for synchronous burst oper- ations: Load Burst Address Valid (ADV#), and Clock (CLK). Each device requires only a single 2.6 Volt-only (2.50 V – 2.75 V) for both read and write func- tions. A 12.0-volt VPP is not required for program or erase operations, although an acceleration pin is available if faster programming performance is required. The device is entirely command set compatible with the JEDEC single-power-supply Flash stan- dard. The software command set is compatible with the command sets of the 5 V Am29F or MBM29F and 3 V Am29LV or MBM29LV Flash families. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an in- ternal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can begin programming or erasing in one bank, and then simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. See Simultaneous Read/Write Opera- tions Overview. The device provides a 256-byte Secured Silicon Sector that contains Electronic Marking Infor- mation for easy device traceability. In addition, the device features several levels of sector protection, which can disable both the pro- gram and erase operations in certain sectors or sector groups: Persistent Sector Protection is a command sector protection method that replaces the old 12 V controlled protection method; Password Sector Protection is a highly sophisticated protection method that requires a pass- word before changes to certain sectors or sector groups are permitted; WP# Hardware Protection prevents program or erase in the two outermost 8 Kbytes sectors of the larger bank. The device defaults to the Persistent Sector Protection mode. The customer must then choose if the Standard or Password Protection method is most desirable. The WP# Hardware Protection feature is always available, independent of the other protection method chosen. The VersatileI/O™ (VCCQ) feature allows the output voltage generated on the device to be de- termined based on the VIO level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on the same bus. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. |
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