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MAX1186 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part No. MAX1186
Description  Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1186 Datasheet(HTML) 5 Page - Maxim Integrated Products

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Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10k
Ω resistor, VIN = 2VP-P (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
VDD
2.7
3.0
3.6
V
Output Supply Voltage Range
OVDD
1.7
2.5
3.6
V
Operating, fINA or B = 20MHz at -0.5dB FS
35
50
Sleep mode
2.8
mA
Analog Supply Current
IVDD
Shutdown, clock idle, PD = OE = OVDD
115
µA
Operating, CL = 15pF, fINA or B = 20MHz at
-0.5dB FS
4mA
Sleep mode
100
Output Supply Current
IOVDD
Shutdown, clock idle, PD = OE = OVDD
210
µA
Operating, fINA or B = 20MHz at -0.5dB FS
105
150
Sleep mode
8.4
mW
Power Dissipation
PDISS
Shutdown, clock idle, PD = OE = OVDD
345
µW
Offset
±0.2
mV/V
Power-Supply Rejection Ratio
PSRR
Gain
±0.1
%/V
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
tDOA
Figure 3 (Note 3)
5
8
ns
CLK Fall to CHB Output Data
Valid
tDOB
Figure 3 (Note 3)
5
8
ns
Clock Rise/Fall to A/B Rise/Fall
Time
tDA/B
6ns
Output Enable Time
tENABLE
Figure 4
10
ns
Output Disable Time
tDISABLE
Figure 4
1.5
ns
CLK Pulse Width High
tCH
Figure 3, clock period: 25ns
12.5
±3.8
ns
CLK Pulse Width Low
tCL
Figure 3, clock period: 25ns
12.5
±3.8
ns
Wake-up from sleep mode (Note 4)
0.41
Wake-Up Time
tWAKE
Wake-up from shutdown (Note 4)
1.5
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
fINA or B = 20MHz at -0.5dB FS
-70
dB
Gain Matching
fINA or B = 20MHz at -0.5dB FS
0.02
±0.2
dB
Phase Matching
fINA or B = 20MHz at -0.5dB FS
0.25
degrees
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to VIH and VIL. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.


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