MAX1186 datasheet(11/21 Pages) MAXIM | Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

Part No.	MAX1186

Description	Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

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Detailed Description

The MAX1186 uses a nine-stage, fully-differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consumption.

Samples taken at the inputs move progressively through

the pipeline stages every one-half clock cycle. Including

the delay through the output latch, the total clock-cycle

latency is five clock cycles.

1.5-bit (2-comparator) flash ADCs convert the held input

voltages into a digital code. The digital-to-analog con-

verters (DACs) convert the digitized results back into

analog voltages, which are then subtracted from the

original held input signals. The resulting error signals

are then multiplied by two and the residues are passed

along to the next pipeline stages, where the process is

repeated until the signals have been processed by all

nine stages. Digital error correction compensates for

ADC comparator offsets in each of these pipeline

stages and ensures no missing codes.

Both input channels are sampled on the rising edge of

the clock and the resulting data is multiplexed at the

output. CHA data is updated on the rising edge (5 clock

cycles later) and CHB data is updated on the falling

edge (5.5 clock cycles later) of the clock signal. The A/B

indicator follows the clock signal with a typical delay

time of 6ns and remains high when CHA data is updat-

ed and low when CHB data is updated.

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the

input track-and-hold (T/H) circuits in both track- and hold-

mode. In track mode, switches S1, S2a, S2b, S4a, S4b,

S5a, and S5b are closed. The fully-differential circuits

sample the input signals onto the two capacitors (C2a

and C2b) through switches S4a and S4b. S2a and S2b

set the common mode for the amplifier input, and open

simultaneously with S1, sampling the input waveform.

Switches S4a and S4b are then opened before switches

S3a and S3b connect capacitors C1a and C1b to the out-

put of the amplifier and switch S4c is closed. The result-

ing differential voltages are held on capacitors C2a and

C2b. The amplifiers are used to charge capacitors C1a

and C1b to the same values originally held on C2a and

C2b. These values are then presented to the first stage

quantizers and isolate the pipelines from the fast-chang-

ing inputs. The wide input bandwidth T/H amplifiers allow

the MAX1186 to track and sample/hold analog inputs of

high frequencies (> Nyquist). Both ADC inputs (INA+,

INB+, INA-, and INB-) can be driven either differentially or

single-ended. Match the impedance of INA+ and INA-,

as well as INB+ and INB-, and set the common-mode

voltage to midsupply (VDD/2) for optimum performance.

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________

11

T/H

VOUT

x2

Σ

FLASH

ADC

DAC

1.5 BITS

10

VINA

VIN

STAGE 1

STAGE 2

DIGITAL CORRECTION LOGIC

STAGE 8

STAGE 9

2-BIT FLASH

ADC

T/H

VOUT

x2

Σ

FLASH

ADC

DAC

1.5 BITS

10

VINB

VIN

STAGE 1

STAGE 2

DIGITAL CORRECTION LOGIC

STAGE 8

STAGE 9

2-BIT FLASH

ADC

T/H

OUTPUT

MULTIPLEXER

10

D0A/B–D9A/B

Figure 1. Pipelined Architecture—Stage Blocks

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