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IDT72T51253L5BBI Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72T51253L5BBI Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 55 page 8 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits OE OutputEnable HSTL-LVTTL in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be (Continued) INPUT inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpoint OEprovidesthree- (M14) state of that respective device. OV OutputValid HSTL-LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice (P9) Flag OUTPUT data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OVflag represents the data in that respective queue. When a selected queue on the read port is read to empty, the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High- Impedance capability, required when multiple devices are used and the OV flags are tied together. OW(1) OutputWidth LVTTL OW selects the bus width for the data output bus. If OW is LOW during a Master Reset then the bus width (L16) INPUT is x18, if HIGH then it is x9. PAE Programmable HSTL-LVTTL This pin provides the Almost-Empty flag status for the queue that has been selected on the output port (P10) Almost-Empty OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected Flag queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is synchronized to RCLK. PAEn Programmable HSTL-LVTTL On the 4Q device the PAEn bus is 8 bits wide. During a Master Reset this bus is setup for Almost Empty ( PAE3-P13 Almost-Empty OUTPUT mode.Thisoutputbusprovides PAEstatusof4queueswithinaselecteddevice.Duringqueueread/write PAE2-R13 Flag Bus operations these outputs provide programmable empty flag status, in either direct or polled mode. The PAE1-T13 modeofflagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapable PAE0-T14) of High-Impedance state, this is important during expansion of multi-queue devices. During direct operation the PAEnbusisupdatedtoshowthePAEstatusofqueueswithinaselecteddevice.Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEnbusisloadedwiththePAE status of multi-queue flow-control devices sequentially based on the rising edge of RCLK. PAF Programmable HSTL-LVTTL ThispinprovidestheAlmost-Fullflagstatusforthequeuethathasbeenselectedontheinputportforwrite (R8) Almost-FullFlag OUTPUT operations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselectedqueueisalmost- full. This flag output may be duplicated on one of the PAFnbuslines.ThisflagissynchronizedtoWCLK. PAFn Programmable HSTL-LVTTL On the 4Q device the PAFn bus is 8 bits wide. This output bus provides PAF status of 4 queues within ( PAF3-P5 Almost-FullFlag OUTPUT a selected device. During queue read/write operations these outputs provide programmable full flag PAF2-R5 Bus status, in either direct or polled mode. The mode of flag operation is determined during master reset via PAF1-T5 thestateoftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansion PAF0-T4) ofmulti-queuedevices.Duringdirectoperationthe PAFnbusisupdatedtoshowthePAFstatusofqueues within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFnbusisloadedwiththe PAF statusofmulti-queueflow-controldevicessequentially based on the rising edge of WCLK. PD Power Down HSTL This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL (K1) INPUT mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power savings. In LVTTL mode this pin has no operation PRS PartialReset HSTL-LVTTL APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial (T8) INPUT Reset can be performed on a queue, that queue must be selected on both the write port and read port 2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to the first memory location, none of the devices configuration will be changed. Q[17:0] Data Output Bus HSTL-LVTTL These are the 18 data output pins. Data is read out of the device via these output pins on the rising edge Qout (See Pin OUTPUT of RCLK provided that REN is LOW, OE is LOW and the queue is selected. Due to bus matching not table for details) all outputs may be used, any unused outputs should not be connected. RADEN Read Address HSTL-LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to (R14) Enable INPUT be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note, that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part has been completed and SENO has gone LOW. PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Description Pin No. |
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