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S29CD-G Datasheet(PDF) 34 Page - SPANSION |
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S29CD-G Datasheet(HTML) 34 Page - SPANSION |
34 / 87 page 32 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Prel imi n ary Table 33. Configuration Register Definitions CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 RM ASD IAD3 IAD2 IAD1 IAD0 DOC WC CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 BS CC Reserved Reserved Reserved BL2 BL1 BL0 Configuration Register CR15 = Read Mode (RM) 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) CR14 = Reserved for Future Enhancements 0 = ASM enable 1 = ASM disable CR13–CR10 = Automatic Sleep Mode Disable Speed Options 40, 56, and 66 MHz: 0000 = 2 CLK cycle initial burst access delay 0001 = 3 CLK cycle initial burst access delay 0010 = 4 CLK cycle initial burst access delay 0011 = 5 CLK cycle initial burst access delay 0100 = 6 CLK cycle initial burst access delay 0101 = 7 CLK cycle initial burst access delay 0110 = 8 CLK cycle initial burst access delay 0111 = 9 CLK cycle initial burst access delay—Default CR9 = Data Output Configuration (DOC) 0 = Hold Data for 1-CLK cycle—Default 1 = Reserved CR8 = IND/WAIT# Configuration (WC) 0 = IND/WAIT# Asserted During Delay—Default 1 = IND/WAIT# Asserted One Data Cycle Before Delay CR7 = Burst Sequence (BS) 0 = Reserved 1 = Linear Burst Order—Default CR6 = Clock Configuration (CC) 0 = Reserved 1 = Burst Starts and Data Output on Rising Clock Edge—Default CR5–CR3 = Reserved For Future Enhancements (R) These bits are reserved for future use. Set these bits to 0. CR2–CR0 = Burst Length (BL2–BL0) 000 = Reserved, burst accesses disabled (asynchronous reads only) 001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear 010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear 011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default) 100 = Reserved, burst accesses disabled (asynchronous reads only) 101 = Reserved, burst accesses disabled (asynchronous reads only) 110 = Reserved, burst accesses disabled (asynchronous reads only) |
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