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S29CD016J Datasheet(PDF) 3 Page - SPANSION

Part No. S29CD016J
Description  16 Megabit (512k x 32-Bit) CMOS 2.6 or 3.3 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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Maker  SPANSION [SPANSION]
Homepage  http://www.spansion.com
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S29CD016J Datasheet(HTML) 3 Page - SPANSION

 
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September 20, 2006 Revision A2
S29CD016J/S29CL016J Known Good Die
3
Supplement
(Adv an ce
Inf o r m atio n)
S29CD/CL016J Features
The S29CD016J & S29CL016J Flash devices are burst mode, dual boot, simultaneous read/write Flash
memories with VersatileI/O™ manufactured on 110 nm process technology.
The S29CD016J is a 16 megabit, 2.6 volt-only, single-power-supply, burst mode Flash memory device that
can be configured for 524,288 double words. The S29CL016J is the 3.3 volt-only version of that device. Both
devices can be programmed in standard EPROM programmers.
To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls. Additional control inputs are required for synchronous burst operations: Load Burst
Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.6 volt-only (2.50 V – 2.75 V) or 3.3 volt-only (3.00 V – 3.60 V) for both
read and write functions. A 12.0-volt VPP is not required for program or erase operations, although an
acceleration pin is available if faster programming performance is required.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The
software command set is compatible with the command sets of the 5 V Am29F and 3 V Am29LV Flash
families. Commands are written to the command register using standard micro-processor write timing.
Register contents serve as inputs to an internal state-machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the programming and erase
operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program
data instead of four.
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space
into two banks. The device can begin programming or erasing in one bank, and then simultaneously read
from the other bank, with zero latency. This releases the system from waiting for the completion of program or
erase operations.
The device provides a 256-byte Secured Silicon Sector with an one-time-programmable (OTP) mechanism.
In addition, the device features several levels of sector protection, which can disable both the program and
erase operations in certain sectors or sector groups: Persistent Sector Protection is a command sector
protection method that replaces the old 12 V controlled protection method; Password Sector Protection is a
highly sophisticated protection method that requires a password before changes to certain sectors or sector
groups are permitted; WP# Hardware Protection prevents program or erase in the two outermost 8 Kbytes
sectors of the larger bank.
The device defaults to the Persistent Sector Protection mode. The customer must then choose if the
Standard or Password Protection method is most desirable. The WP# Hardware Protection feature is always
available, independent of the other protection method chosen.
The VersatileI/O™ (VCCQ) feature allows the output voltage generated on the device to be determined based
on the VIO level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving
signals to and from other 1.8 V devices on the same bus.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,
by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle has been
completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. The password and software sector protection feature disables both program and
erase operations in any combination of sectors of memory. This can be achieved in-system at VCC level.
The Program/Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of
time to read data from, or program data to, any sector that is not selected for erasure. True background erase
can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to
reading array data.


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