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AM29BDS643G Datasheet(PDF) 4 Page - SPANSION

Part No. AM29BDS643G
Description  64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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Maker  SPANSION [SPANSION]
Homepage  http://www.spansion.com
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AM29BDS643G Datasheet(HTML) 4 Page - SPANSION

 
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Am29BDS643G
25692A2 May 8, 2006
D A TA
SH EE T
GENERAL DESCRIPTION
The Am29BDS643G is a 64 Mbit, 1.8 Volt-only, simul-
taneous Read/Write, Burst Mode Flash memor y
device, organized as 4,194,304 words of 16 bits each.
This device uses a single VCC of 1.7 to 1.9 V to read,
program, and erase the memory array. A 12.0-volt VPP
may be used for faster program performance if desired.
The device can also be programmed in standard
EPROM programmers.
At 66 MHz, the Am29N643 provides a burst access of
11 ns at 30 pF with initial access times of 71 ns at 30
pF. At 54 MHz, the device provides a burst access of
13.5 ns at 30 pF with initial access times of 87.5 ns at
30 pF. At 40 MHz, the device provides a burst access
of 20 ns at 30 pF with initial access times of 95 ns at 30
pF. The device operates within the industrial tempera-
ture range of –40
°C to +85°C. The device is offered in
the 44-ball Very Thin FBGA package.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into four banks. The device allows a host sys-
tem to pr og r a m or er a s e in on e b a n k , th en
immediately and simultaneously read from another
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The device is divided as shown in the following table:
The device uses Chip Enable (CE#), Write Enable
(WE#), Address Valid (AVD#) and Output Enable
(OE#) to control asynchronous read and write opera-
tions. For burst operations, the device additionally
requires Power Saving (PS), Ready (RDY), and Clock
(CLK). This implementation allows easy interface with
minimal glue logic to microprocessors/microcontrollers
for high performance read operations.
The device offers complete compatibility with the
JEDEC 42.4 single-power-supply Flash command
set standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle
bits). After a program or erase cycle has been com-
pleted, the device automatically returns to reading
array data.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The device also offers
three types of data protection at the sector level. The
sector lock/unlock command sequence disables or
re-enables both program and erase operations in any
sector. When at VIL, WP# locks the outermost sectors.
Finally, when VPP is at VIL, all sectors are locked.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Bank A & B Sectors
Bank C & D Sectors
Quantity
Size
Quantity
Size
48 Kwords
32
32 Kwords
31
32 Kwords
32 Mbits total
32 Mbits total


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