74AUP2G38GT datasheet(2/16 Pages) PHILIPS

Part #	74AUP2G38GT

Description	Low-power dual 2-input NAND gate (open-drain)

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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2 / 16 page

74AUP2G38_1

Product data sheet

Rev. 01 — 16 October 2006

2 of 16

NXP Semiconductors

74AUP2G38

Low-power dual 2-input NAND gate (open-drain)

3.

Ordering information

4.

Marking

5.

Functional diagram

6.

Pinning information

6.1 Pinning

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74AUP2G38DC

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74AUP2G38GT

−40 °C to +125 °C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

× 1.95 × 0.5 mm

SOT833-1

74AUP2G38GM

−40 °C to +125 °C

XQFN8

plastic extremely thin quad ﬂat package; no leads; 8

terminals; body 1.6

× 1.6 × 0.5 mm

SOT902-1

Table 2.

Marking

Type number

Marking code

74AUP2G38DC

a38

74AUP2G38GT

a38

74AUP2G38GM

a38

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

mnb129

1A

1B

1Y

2

1

7

2A

2B

2Y

6

5

3

2

7

&

1

6

3

&

5

mnb130

mnb131

Y

GND

B

A

Fig 4.

Pin conﬁguration SOT765-1 (VSSOP8)

74AUP2G38

1A

VCC

1B

1Y

2Y

2B

GND

2A

001aaf547

1

2

3

4

6

5

8

7

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