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XC7A35T-1CPG236C Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # XC7A35T-1CPG236C
Description  Cmod A7 Reference Manual
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Cmod A7 Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 5 of 10
device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a
circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this
complexity is hidden from the user by the Xilinx tools). This is called indirect programming. After the flash device
has been programmed, it can automatically configure the FPGA at a subsequent power-on event. Programming
files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process
inherent to the memory technology. Once written, however, FPGA configuration can be very fast—less than a
second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that
can affect configuration speed. The Cmod A7 supports x1, x2, and x4 bus widths and data rates of up to 50 MHz for
Quad-SPI programming.
Quad-SPI programming can be done using the hardware manager in Vivado.
The Cmod A7 includes 512 KB of Static Random-Access Memory (SRAM). This memory has a standard, easy-to-use
parallel interface with 19 address signals, 8 bi-directional data signals, and 3 control signals. The part used is the
ISSI IS61WV5128BLL-10BLI. The interface is fully documented in ISSI's datasheet for the part.
The power supply used to power the SRAM provides 3.3V with greater than 5% accuracy. This allows the
IS61WV5128BLL-10BLI part to be written to and read from with 8 ns access times. This allows for a theoretical
maximum data bandwidth of 125,000,000 B/s.
The onboard SRAM is very useful for MicroBlaze designs that would like to provide the processor with additional
memory. To do this, the SRAM can be controlled with Xilinx External Memory Controller IP core. The Cmod A7 User
demo available on the Cmod A7 resource center demonstrates how to do this.
For pin-mappings between the FPGA and SRAM, please see the CmodA7 Master XDC available on the Cmod A7
Resource Center.
Quad-SPI Flash
FPGA configuration files can be written to the Quad-SPI Flash (Micron part number N25Q032A) and the FPGA will
automatically configure itself with it after power on (as described in section 2.2). An Artix-7 35T or 15T
configuration file requires 17,536,096 bits of memory, leaving about half of the flash device (just over 2MB)
available for user data. A common use for this extra memory is to store MicroBlaze programs too big to fit in the
on-chip Block memory (typically 128 KB for the 35T and 64KB for the 15T). These programs are then loaded and
executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically
generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your
custom MicroBlaze application, and program this file into SPI Flash using Xilinx SDK and Vivado. Xilinx Answer
Record 63605 explains how to do this.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation
of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins
after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after
configuration, however, on the Cmod A7 the SCK signal is routed to an additional general purpose pin that can be

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