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LMX2332U Datasheet(PDF) 31 Page - National Semiconductor (TI) |
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LMX2332U Datasheet(HTML) 31 Page - National Semiconductor (TI) |
31 / 42 page 1.0 Functional Description (Continued) PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 10136611 Notes: 1. The minimum width of the pump-up and pump-down current pulses occur at the Do RF or Do IF pins when the loop is phase locked. 2. The diagram assumes positive VCO characteristics, i.e. PD_POL RF or PD_POL IF = 1. 3. Fr is the phase detector input from the reference divider (R counter). 4. Fp is the phase detector input from the programmable feedback divder (N counter). 5. Do refers to either the RF or IF charge pump output. 1.6 CHARGE PUMPS The charge pump directs charge into or out of an external loop filter. The loop filter converts the charge into a stable control voltage which is applied to the tuning input of the VCO. The charge pump steers the VCO control voltage towards V P RF or VP IF during pump-up events and towards GND during pump-down events. When locked, D o RF or Do IF are primarily in a TRI-STATE mode with small corrections occuring at the phase comparator rate. The charge pump output current magnitude can be selected by toggling the ID o RF or ID o IF control bits. 1.7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed via the MI- CROWIRE serial interface. The interface is comprised of three signal pins: Clock, Data and LE (Latch Enable). Serial data is clocked into the 22-bit shift register on the rising edge of Clock. The last two bits decode the internal control regis- ter address. When LE transitions HIGH, data stored in the shift register is loaded into one of four control registers depending on the state of the address bits. The MSB of Data is loaded in first. The synthesizers can be programmed even in power down mode. A complete programming description is provided in Section 2.0 Programming Description. 1.8 MULTI-FUNCTION OUTPUTS The LMX233xU device’s F oLD output pin is a multi-function output that can be configured as the RF FastLock output, a push-pull analog lock detect output, counter reset, or used to monitor the output of the various reference divider (R counter) or feedback divider (N counter) circuits. The F oLD control word is used to select the desired output function. When the PLL is in powerdown mode, the F oLD output is pulled to a LOW state. A complete programming description of the multi-function output is provided in Section 2.8 F oLD. 1.8.1 Push-Pull Analog Lock Detect Output An analog lock detect status generated from the phase detector is available on the F oLD output pin if selected. The lock detect output goes HIGH when the charge pump is inactive. It goes LOW when the charge pump is active during a comparison cycle. When viewed with an oscilloscope, narrow negative pulses are observed when the charge pump turns on. The lock detect output signal is a push-pull con- figuration. Three separate lock detect signals are routed to the multi- plexer. Two of these monitor the ‘lock’ status of the individual synthesizers. The third detects the condition when both the RF and IF synthesizers are in a ‘locked state’. External circuitry however, is required to provide a steady DC signal to indicate when the PLL is in a locked state. Refer to Section 2.8 F oLD for details on how to program the different lock detect options. www.national.com 31 |
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