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MF007M5-03ATXX Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor

Part No. MF007M5-03ATXX
Description  8/16-bit Data Bus Flash ATA PC Card
Download  29 Pages
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MF007M5-03ATXX Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor

 
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MITSUBISHI STORAGE CARD
ATA PC CARDS
MITSUBISHI
ELECTRIC
4
1997.Nov. Rev. 1.2
Attribute Memory Select[REG#]
(PC Card Memory Mode)
I
61
When this signal is asserted, access is limited to
Attribute Memory with OE#/WE# and I/O Space with
Attribute Memory Select[REG#]
(PC Card I/O Mode)
IORD#/IOWR#.
Attribute Memory Select[REG#]
(IDE ATA Interface)
This input signal is not used for this mode and
should be connected to Vcc by the host.
Battery Voltage Detect[BVD2]
(PC Card Memory Mode)
O
62
This output is driven to a high-level.
Audio Digital Waveform[SPKR#]
(PC Card I/O Mode)
SPKR# is kept negated because this Card does not
have digital audio output.
DASP#
(IDE ATA Interface)
I/O
This signal is the DISK Active/Slave Present signal
in the Master/Slave handshake protocol.
Card Reset[RESET]
(PC Card Memory Mode)
I
58
By assertion of this signal, all registers of this Card
are cleared. This signal should be kept to High-Z by
Card Reset[RESET]
(PC Card I/O Mode)
the host for at least 1ms after Vcc applied.
Card Reset[RESET#]
(IDE ATA Interface)
This input pin is the active low hardware reset from
the host.
Wait[WAIT#]
(PC card Memory Mode)
O
59
This signal is asserted to delay completion of the
memory or I/O access cycle.
Wait[WAIT#]
(PC card I/O Mode)
IORDY
(IDE ATA Interface)
Input Port Acknowledge[INPACK#]
(PC Card I/O Mode)
O
60
This signal is asserted when the Card is selected
and can respond to an I/O Read cycle at the
Input Port Acknowledge[INPACK#]
(IDE ATA Interface)
address on the address bus.
Battery Voltage Detect[BVD1]
(PC Card Memory Mode)
O
63
This output is driven to a high-level.
STSCHG#
(PC Card I/O Mode)
This signal is asserted low to alert the host to
changes in the status of Configuration Status
Register in the Attribute Memory Space.
PDIAG#
(IDE ATA Interface)
I/O
This signal is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
Voltage Sense[VS1, VS2]
O
43, 57
VS1 is grounded so that the Card CIS can be read
at 3.3V and VS2 is N.C.
Cable Select[CSEL]
(PC card Memory Mode)
-
56
This signal is not used for this mode.
Cable Select[CSEL]
(PC card I/O Mode)
-
Cable Select[CSEL]
(IDE ATA Interface)
I
This signal is used to configure this Card as a
Master or a Slave. When this signal is grounded,
this Card is configured as a Master. When this
signal is Open, this Card is configure as a Slave.
Vcc
-
17, 51
5V or 3.3V power.
GND
-
1, 34, 35, 68
Ground.


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