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DP83222 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DP83222 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 12 page 10 Functional Description (Continued) The result from XOR-D is a hypothetical data sequence HD that should match the original unscrambled NRZ IDLE data barring any noise events The Boolean progression in Figure 4 demonstrates that HD should equal the original unscram- bled IDLE bits Over time Register H is loaded with the hypothetical data sequence HD Before the Line State Monitor detects a valid IDLE se- quence (no less than 50 consecutive IDLE bits) the Stream Cipher logic remains in the Sample mode While in Sample mode the MUX select input ‘‘sel’’ routes the ‘‘in sample’’ input to Register B The MUX input ‘‘in sample’’ is con- nected to the original SD datastream which continuously loads and updates Register B so that its contents dynami- cally match Register A This dynamic match is important as it ensures synchronization with the LFSR in the scrambler section When the Line State Monitor logic within the Register H block recognizes sufficient consecutive IDLE bits it will out- put a Hold Flag HF which controls the MUX feeding Regis- ter B When HF becomes true the MUX ‘‘in hold’’ input is selected which routes the LDD data sequence back into Register B This configures Register B and XOR-E into an LFSR (identical to that in the scrambler logic in Section 12) Register B now an LFSR is synchronized with the incoming datastream SD allowing XOR-F to descramble SD by a simple XOR function with LDD To ensure continuous syn- chronization for valid conditions the Hold Timer in the Reg- ister H block will hold HF true for a sufficient time until more IDLE bits can be decoded which resets the timer The Hold Timer time-out period is based on the maximum time under normal operation between IDLE occurrences (l722 ms) If IDLE symbols cease to be decoded the Hold Timer will time out forcing HF false This will cause the stream cipher to fall into the sample mode again awaiting further valid line states for resynchronization This analysis is intended to provide a general understanding of the mechanisms involved in the stream cipher process Some circuit details were omitted for simplification A more detailed logical and Boolean description of the stream ci- pher process is generally available 14 STREAM CIPHER BOOLEAN The following Boolean analysis supports the stream cipher logic for IDLE reception example stated herein Given that the character denotes an exclusive OR func- tion UD n e Unscrambled Data (‘‘IDLE’’ ones) LDS n e Scrambler’s LFSR feedback data (Pseudo Ran- dom) SD n e scrambled data (LDS n UD n ) SD n e result of XOR-C HD n e Hypothetical Data (SD n SD n ) HF e Hold Flag LDD n e Descrambler LFSR feedback data DD n e Descrambled Data (SD n LDD n ) Since LDS n e (LDS n-9 LDS n-11 ) Then SD e (UD n LDS n ) And Since UD n e 1 IDLE bits Then SD n e LDS n Since SD n e SD n-9 SD n-11 And SD n e (LDS n-9 LDS n-11 ) Then SD n e (LDS n-9 LDS n-11 ) e LDS n And Since SD n e LDS n Then HD n e (SD n SD n ) e (LDS n LDS n ) e 1 IDLE bits If HF e 1due to the detection of sufficient valid IDLE symbols And LDD n e LDS n because LDD dynamically tracks LDS And Since DD n e (LDS n SD) e (LDS n UD n LDS n ) Then DD n e UD n FIGURE 4 Stream Cipher Boolean Analysis 4 |
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