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ISPLSI5256VE-80LT100I Datasheet(PDF) 11 Page - Lattice Semiconductor

Part # ISPLSI5256VE-80LT100I
Description  In-System Programmable 3.3V SuperWIDE High Density PLD
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPLSI5256VE-80LT100I Datasheet(HTML) 11 Page - Lattice Semiconductor

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Specifications ispLSI 5256VE
11
Switching Test Conditions
Input Pulse Levels
Table 2-0003/5KVE
Input Rise and Fall Time
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
GND to VCCIOmin
≤ 1.5ns 10% to 90%
1.5V
1.5V
See Figure 9
3-state levels are measured 0.5V from
steady-state active level.
Output Load Conditions (See Figure 9)
TEST CONDITION
R1
3.3V
2.5V
R2
CL
A
35pF
D
35pF
B
35pF
35pF
Active High
Slow Slew
Active Low
C
5pF
5pF
511Ω
∞
∞
511Ω
511Ω
∞
475Ω
∞
475Ω
∞
∞
475Ω
R1
R2
316Ω
∞
∞
316Ω
316Ω
∞
348Ω
∞
348Ω
∞
∞
348Ω
Active Low to Z
at V +0.5V
OL
Active High to Z
at V
-0.5V
OH
Table 2-0004A/5KVE
DC Electrical Characteristics for 3.3V Range
1
Over Recommended Operating Conditions
Figure 9. Test Load
VCCIO
R1
R2
CL*
Device
Output
Test
Point
*CL includes Test Fixture and Probe Capacitance.
0213D
VOL
SYMBOL
1. I/O voltage configuration must be set to VCC.
Table 2-0007/5KVE
VOH
VIH
VIL
PARAMETER
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
VCCIO = min, IOL = 8 mA
VCCIO = min, IOH = -4 mA
CONDITION
MIN.
TYP.
MAX.
UNITS
–
2.4
2.0
-0.3
–
–
–
–
0.4
–
5.25
0.8
V
V
VCCIO
I/O Reference Voltage
3.0
–
3.6
V
V
V


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