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MF0064M-07ATXX Datasheet(PDF) 16 Page - Mitsubishi Electric Semiconductor |
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MF0064M-07ATXX Datasheet(HTML) 16 Page - Mitsubishi Electric Semiconductor |
16 / 32 page MITSUBISHI STORAGE CARD Preliminary ATA PC CARDS MITSUBISHI ELECTRIC 16 Oct.1999 Rev. 0.2 Drive/Head Register The Drive/Head register is used to specify the selected drive of a pair of drives sharing a set of registers. D7 D6 D5 D4 D3 D2 D1 D0 X LBA X DRV HS3 HS2 HS1 HS0 LBA27 LBA26 LBA25 LBA24 Field function X Undefined . “0” or “1”. LBA This bit is “0” for CHS addressing and “1” for Logical Block addressing. DRV This bit is number of the drive which the host has selected. When DRV is cleared, Drive0 is selected. When DRV is set, Drive1 is selected. The card is selected to be Drive0 or to be Drive1 using the “Copy” field of the PC Card Socket Copy Register. HS3-0 LBA27-24 HS3-0 of the head number in CHS addressing or LBA27-24 of the Logical Block Number in LBA addressing. Status and Alternate Status Registers The Status register and the Alternate Status register return the card status when read by the host. Reading the Status register clears a pending interrupt request while reading the Alternate Status register does not. The Status register and the Alternate Status register are read only registers. D7 D6 D5 D4 D3 D2 D1 D0 BSY DRDY DWF DSC DRQ CORR IDX ERR Field function BSY This bit is set when the card internal operation is executing. When this bit is set to “1”, other bits in this register are invalid. DRDY DRDY indicates whether the card is capable of performing card operations. DWF This bit, if set, indicates a write fault has occurred. DSC This bit is set when the drive seek complete. DRQ This bit is set when the information can be transferred between the host and Data register. CORR This bit is set when a correctable data error has been occurred and the data has been corrected. IDX This bit is always set to “0”. ERR This bit is set when the previous command has ended in some type of error. The error information is set in the other Status register bits or Error register. This bit is cleared by the next command. Command Register The Command register contains the command code being sent to the device. Command execution begins immediately after this register is written. The Command register is a write only register. D7 D6 D5 D4 D3 D2 D1 D0 Command Device Control Register This register is used to control the card interrupt request and to issue a soft reset to the card. The Device Control register is a write only register. D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 SRST nIEN 0 Field function X don’t care. 1 This bit is set to “1”. SRST This bit is set to “1” in order to force the card to perform a Command Block Reset operation. This does not change the Card Configuration registers as a Hardware Reset does. The card remains in Reset until this bit is reset to “0”. nIEN This bit is used for enabling IREQ#. When this bit is set to “0”, IREQ# is enabled. When this bit is set to “1”, IREQ# is disabled. 0 This bit is set to “0”. Drive Address Register This register is provided for compatibility with the AT disk drive interface. D7 D6 D5 D4 D3 D2 D1 D0 X nWT G nHS3-0 nDS1 nDS0 Field function X This bit is unknown. nWTG This bit is set to “0” when a Flash write operation is in progress, otherwise it is set to “1”. nHS3-0 These bits is the negative value of Head Select bits in Drive/Head register. nDS1 This bit is set to “0” when Slave drive is active and selected. nDS0 This bit is set to “0” when Master drive is active and selected. |
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