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WED8L24514V Datasheet(PDF) 1 Page - White Electronic Designs Corporation

Part No. WED8L24514V
Description  Asynchronous SRAM, 3.3V, 512Kx24
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Maker  WEDC [White Electronic Designs Corporation]
Homepage  http://www.whiteedc.com
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WED8L24514V Datasheet(HTML) 1 Page - White Electronic Designs Corporation

   
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White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WED8L24514V
1
234
56
7
ANC
AO
A1
A2
A3
A4
NC
BNC
A5
A6
E0
A7
A8
NC
C
I/012
NC
E2
NC
E3
NC
I/00
D
I/013
VCC
GND
GND
GND
VCC
I/01
E
I/014
GND
VCC
GND
VCC
GND
I/02
F
I/015
VCC
GND
GND
GND
VCC
I/03
G
I/016
GND
VCC
GND
VCC
GND
I/04
H
I/017
VCC
GND
GND
GND
VCC
I/05
J
NC
GND
VCC
GND
VCC
GND
NC
K
I/018
VCC
GND
GND
GND
VCC
I/06
L
I/019
GND
VCC
GND
VCC
GND
I/07
M
I/020
VCC
GND
GND
GND
VCC
I/08
N
I/021
GND
VCC
GND
VCC
GND
I/09
P
I/022
VCC
GND
GND
GND
VCC
I/010
R
I/023
A18
NC
NC
NC
A17
I/011
TNC
A9
A10
WA11
A12
NC
UNC
A13
A14
GA15
A16
NC
September 2001 Rev. 2
ECO #14670
FIG. 1
PIN NAMES
BLOCK DIAGRAM
PIN SYMBOLS
PIN CONFIGURATION
Asynchronous SR
Asynchronous SR
Asynchronous SR
Asynchronous SR
Asynchronous SRAM, 3.3V
AM, 3.3V
AM, 3.3V
AM, 3.3V
AM, 3.3V, 512Kx24
, 512Kx24
, 512Kx24
, 512Kx24
, 512Kx24
FEATURES
n 512Kx24 bit CMOS Static
n Random Access Memory Array
• Fast Access Times: 10, 12, and 15ns
• Master Output Enable and Write Control
• Three Chip Enables for Byte Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
n Surface Mount Package
• 119 Lead BGA (JEDEC MO-163), No. 391
• Small Footprint, 14mmx22mm
• Multiple Ground Pins for Maximum Noise Immunity
n Single +3.3V (±5%) Supply Operation
n DSP Memory Solution
• Motorola DSP5630x
• Analog Devices SHARCTM
DESCRIPTION
The WED8L24514VxxBC is a 3.3V, twelve megabit SRAM
constructed with three 512Kx8 die mounted on a multi-
layer laminate substrate. With 10 to 15ns access times, x24
width and a 3.3V operating voltage, the WED8L24514V is
ideal for creating a single chip memory solution for the
Motorola DSP5630x or a two chip solution for the Analog
Devices SHARCTM DSP.
The single or dual chip memory solutions offer improved
system per formance by reducing the length of board
traces and the number of board connections compared
to using multiple monolithic devices.
The JEDEC Standard 119 lead BGA provides a 61%
space savings over using three 512Kx8, 400 mil wide
SOJs and the BGA package has a maximum height of 110
mils compared to 148 mils for the SOJ packages.
A0-18
Address Inputs
E
Chip Enable
W
Master Write Enable
G
Master Output Enable
DQ0-23
Common Data Input/Output
VCC
Power (3.3V ±5%)
GND
Ground
NC
No Connection
512K x 24
Memory
Array
19
A0-A18
G
W
E0
E2
E3
DQ0-7
DQ8-15
DQ16-23


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