INGT165B / INGR165B
10/2003 - rev. 2.0
4 of 21
2.2 INGT165B TRANSMITTER PARALLEL INTERFACE
The Transmitter parallel interface is designed to support different operating modes providing a maximum
flexibility for the design of the application interface.
GigaST#R
INGT165B
TRANSMITTER
SDATA
SDATA#
PARGEN
FLAGI
RESET#
VALID
RDCLK
PDATA[35..0]
PARITY
PERR#
LOCK
SYNGEN
Figure 3: GigaSTaR® Transmitter Parallel Interface
2.2.1 Control Signals
RESET# is an asynchronous active low reset signal. After a power-up sequence and activation of the
reference clock, RESET# has to be kept low for at least 1 ms. The link is operational as soon as the
LSYNC# signal of the Receiver is going low.
LOCK = '1' indicates that the internal PLL is locked. If LOCK is de-asserted the Transmitter is not ready.
PARGEN = '1' activates the internal parity generation. In this mode the PARITY input pin is ignored.
An internal parity bit is generated and transmitted.
The positive edge of FLAGI sets an internal flag which is inserted at the end of the data word currently in
transmission. The Receiver decodes the flag out of the serial bit-stream and toggles the level of the
FLAGO output. This signal can be used to mark the end of a data frame.
VALID = '1' indicates to the Transmitter that data are available. With the assertion of VALID the RDCLK
starts to run. PDATA[35..0] is registered at each rising edge of RDCLK. De-asserting VALID disables
RDCLK and stuffing patterns are transmitted over the GigaSTaR® link to maintain synchronization.
PERR#: description see 2.2.2
Note: the SYNGEN input is reserved for optional functions and has to be set to “0”.
2.2.2 Data Interface
The GigaSTaR® parallel data interface is designed to support a variety of application interfaces.
It provides read clock (RDCLK) pulses with a cycle time of 30,3 ns (corresponding to 33MHz) to the
application output buffers like FIFOs, memory devices, ASICs or PLDs.
A data word at the parallel interface consists of 36 data bits. If PARGEN = '0' the transmitting application
has to supply the data's parity at the input PARITY synchronous to the parallel data. PARGEN = '1' logic
high activates internal parity generation and the PARITY input pin is ignored. If the application supplies its
own parity bit (PARGEN is de-asserted), PERR# reports any mismatch between the internally generated
and the external PARITY signal. If this is the case, the internally generated (correct) PARITY is transmitted
with the data word. PERR# is always inactive when PARGEN = '1'. The default value of PERR# after reset
is ‘1’.
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