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DSM2180F390T6 Datasheet(PDF) 8 Page - STMicroelectronics |
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DSM2180F390T6 Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 63 page  DSM2180F3V 8/63 Figure 5. Block Diagram Programmable Logic (PLDs) The DSM family contains two PLDS that may op- tionally run in Turbo or Non-Turbo mode. PLDs op- erate faster (less propagation delay) while in Turbo mode but consume more power than Non- Turbo mode. Non-Turbo mode allows the PLDs to automatically go to standby when no inputs are change to conserve power. The Turbo mode set- ting is controlled at runtime by DSP software. Decode PLD (DPLD). This is programmable log- ic used to select one of the eight individual Flash memory segments or the group of control registers within the DSM device. The DPLD can also option- ally drive external chip select signals on Port D pins. DPLD input signals include: DSP address and control signals, Page Register outputs, DSM Port Pins, CPLD logic feedback. Complex PLD (CPLD). This programmable logic is used to create both combinatorial and sequen- tial general purpose logic. The CPLD contains 16 Output Macrocells (OMCs) and 16 Input Macro- cells (IMCs). PSD Macrocell registers are unique in that that have direct connection to the DSP data bus allowing them to be loaded and read directly by the DSP at runtime. This direct access is good for making small peripheral devices (shifters, counters, state machines, etc.) that are accessed directly by the DSP with little overhead. DPLD in- puts include DSP address and control signals, Page Register outputs, DSM Port Pins, and CPLD feedback. OMCs: The general structure of the CPLD is simi- lar in nature to a 22V10 PLD device with the famil- iar sum-of-products (AND-OR) construct. True and compliment versions of 64 input signals are available to a large AND array. AND array outputs feed into a multiple product-term OR gate within each OMC (up to 10 product-terms for each OMC). Logic output of the OR gate can be passed on as combinatorial logic or combined with a flip- flop within in each OMC to realize sequential logic. OMCs can be used as a buried nodes with feed- back to the AND array or OMC output can be rout- ed to pins on Port B or PortC. IMCs: Inputs from pins on Port B or Port C are routed to IMCs for conditioning (clocking or latch- ing) as they enter the chip, which is good for sam- pling and debouncing inputs. Alternatively, IMCs can pass Port input signals directly to PLD inputs AI04911 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 I/O PORT PC0 PC1 PC3 PC4 PC5 PC6 I/O PORT COMPLEX PLD (CPLD) 16 INPUT MICRO<>CELLS 16 OUTPUT MICRO<>CELLS A B A B A B A B A B A B A B A B B C B C B C B C B C B C B C B C PAGE REG SECURITY LOCK ALLO- CATOR FLASH MEMORY PIN FEEDBACK NODE FEEDBACK DSM2180F3 DSP SYSTEM MEMORY INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP DECODE PLD (DPLD) AND ARRAY EXTERNAL CHIP SELECTS FS0-7 JTAG-ISP TO ALL AREAS OF CHIP B B B B C C C C B C B C B C B C AD0 DSP ADDR AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 PC2 PC7 DSP CONTROL CNTL0 CNTL1 CNTL2 RST\ PD0 PD1 PD2 3 OPTIONAL OUTPUTS TO PORT D PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 DSP DATA 8 SEGMENTS, 16 KB 128 KBytes TOTAL RUNTIME CONTROL CSIOP REGISTER FILE CSIOP POWER MANAGEMENT fs0 fs7 fs6 fs5 fs4 fs3 fs2 fs1 EXTERNAL CHIP SELECTS, ESC0-2 |
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