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HY64UD16162M-DF70I Datasheet(PDF) 2 Page - Hynix Semiconductor |
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HY64UD16162M-DF70I Datasheet(HTML) 2 Page - Hynix Semiconductor |
2 / 11 page HY64UD16162M Series 2 Revision 1.7 March. 2002 This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 1M x 16 bit Low M x 16 bit Low Low Power 1T/1C Low Power 1T/1C SRAM SRAM DESCRIPTION The HY64UD16162M is a 16Mbit 1T/1C SRAM featured by high-speed operation and super low power consumption. The HY64UD16162M adopts one transistor memory cell and is organized as 1,048,576 words by 16bits. The HY64UD16162M operates in the extended range of temperature and supports a wide operating voltage range. The HY64UD16162M also supports the deep power down mode for a super low standby current. The HY64UD16162M delivers the high-density low power SRAM capability to the high-speed low power system. • CMOS Process Technology • 1M x 16 bit Organization • TTL compatible and Tri-state outputs • Deep Power Down : Memory cell data hold invalid • Standard pin configuration : 48-FBGA • Data mask function by /LB, /UB PRODUCT FAMILY FEATURES Note 1. tCS - /UB,/LB=High : Chip Deselect. Product No. Voltage [V] Speed tRC[ns] Temp. [ °C] (ISB1,Max) (IDPD,Max) (ICC2,Max) Power Dissipation Mode HY64UD16162M-DF70I 2.7~3.3 70 -40~85 85 µA 2 µA 25mA 1CS with /UB,/LB:tCS1 HY64UD16162M-DF70E 2.7~3.3 70 -25~85 85 µA 2 µA 25mA 1CS with /UB,/LB:tCS1 HY64UD16162M-DF85I 2.7~3.3 85 -40~85 75 µA 2 µA 20mA 1CS with /UB,/LB:tCS1 HY64UD16162M-DF85E 2.7~3.3 85 -25~85 75 µA 2 µA 20mA 1CS with /UB,/LB:tCS1 PIN DESCRIPTION Pin Name Pin Function Pin Name Pin Function /CS1 Chip Select IO1~IO8 Lower Data Inputs/Outputs /WE Write Enable A0~A19 Address Inputs /OE Output Enable Vdd Power(2.7V~3.3V) /LB Lower Byte(IO1~IO8) Vss Ground /UB Upper Byte(IO9~IO16) CS2 Deep Power Down DNU Do Not Use IO9~IO16 Upper Data Inputs/Outputs NC No Connection PIN CONNECTION (Top View) BLOCK DIAGRAM ROW DECODER MEMORY ARRAY 1,024K x 16 CONTROL LOGIC A0 A19 IO1 IO8 IO9 IO16 /CS1 CS2 /OE /LB /UB /WE /LB /OE A0 A1 A2 CS2 IO9 /UB A3 A4 /CS1 IO1 IO10 IO11 A5 A6 IO2 IO3 Vss IO12 A17 A7 IO4 Vdd Vdd IO13 DNU A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 IO16 A19 A12 A13 /WE IO8 A18 A8 A9 A10 A11 NC |
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