HY64LD16162M Series

1

Revision 1.7

March. 2002

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not

assume any responsibility for use of circuits described. No patent licenses are implied.

Document Title

Document Title

1

Pseudo SRAM

Revision history

Revision history

Revision No.

Revision No.

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

History

History

Initial

Revised

- Change Pin Connection

- Improve tOE from 45ns to 30ns

- Correct State Diagram

Revised

- Correct Package Dimension

- Change Absolute Maximum Ratings

Revised

- State Diagram

- Power Up Sequence

- Deep Power Down Sequence

- Read/Write Cycle Note

Revised

- DC Electrical Characteristics ( ICC1: 3mA - > 5mA)

Revised

- Power Up Sequence

Revised

- Improve ISB1 80uA to 75uA

- Improve ICC2 30mA to 20mA

- Improve Ambient Temperature C/E to E/I

(0

°C~85°C/-25°C~85°C → -25°C~85°C/-40°C~85°C)

- Improve Maximum Absolute Ratings

(Vdd : -0.3V to 3.3V

→ -0.3V to 3.6V)

- Improve tOE 30ns to 20ns

Revised

- Pin Description

- Power Up & Deep Power Down Exit Sequence

Draft Date

Draft Date

Jan. 04. ’ 01

Jul. 03. ’ 01

Jul.18. ’ 01

Oct. 07. ‘ 01

Nov. 14. ’ 01

Dec. 20. ‘ 01

Feb. 27. ‘ 02

Mar. 11. ‘ 02

Remark

Remark

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

Final