HY62UF16806B

Rev.01/Mar. 2002

7

Notes:

1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a Low /UB and/or /LB.

2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the

end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the

output must not be applied.

4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low

transition or after the /WE transition, outputs remain in a high impedance state.

5. Q(data out) is the same phase with the write data of this write cycle.

6. Q(data out) is the read data of the next address.

7. Transition is measured + 200mV from steady state.

This parameter is sampled and not 100% tested.

8. /CS1 in high for the standby, low for active

CS2 in low for the standby, high for active.

/UB and /LB in high for the standby, low for active

DATA RETENTION ELECTRIC CHARACTERISTIC

°C to 70°C / -40°C to 85°C

Symbol

Parameter

Test Condition

Min

Typ

1.

Max

Unit

Vcc for Data Retention

/CS1 > Vcc - 0.2V or

CS2 < Vss + 0.2V or

/UB, /LB > Vcc - 0.2V,

1.2

-

3.3

V

Iccdr

Data Retention Current

Vcc=1.5V,

/CS1 > Vcc - 0.2V or

CS2 < Vss + 0.2V or

/UB, /LB > Vcc - 0.2V

LL

-

1.0

6

uA

tCDR

Chip Deselect to Data

Retention Time

0

-

-

ns

tR

Operating Recovery Time

See Data Retention Timing Diagram

tRC

-

-

ns

Notes:

°C .

2. tRC is read cycle time.