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PSD4255G2V-10UII Datasheet(PDF) 1 Page - STMicroelectronics |
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PSD4255G2V-10UII Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 100 page 1/100 PRELIMINARY DATA December 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs FEATURES SUMMARY PSD provides an integrated solution to 16-bit MCU-based applications that includes config- urable memories, PLD logic, and I/O: s Dual bank Flash memories – 8Mbits of Primary Flash Memory (16 uniform sectors, 64Kbyte) – 512Kbits of Secondary Flash Memory with 4 sectors – Concurrent operation: READ from one mem- ory while erasing and writing the other s 256Kbits of SRAM (battery-backed) s PLD with Macrocells – Over 3000 Gates of PLD: CPLD and DPLD – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) – DPLD - user defined internal chip select de- coding s Seven l/O Ports with 52 I/O pins: 52 individually configurable I/O port pins that can be used for the following functions: – MCU I/Os –PLD I/Os – Latched MCU address output – Special function I/Os – l/O ports may be configured as open-drain outputs s In-System Programming (ISP) with JTAG – Built-in JTAG compliant serial port allows full- chip In-System Programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC s Page Register – Internal page register that can be used to ex- pand the microcontroller address space by a factor of 256 s Programmable power management s High Endurance: – 100,000 Erase/WRITE Cycles of Flash Mem- ory – 1,000 Erase/WRITE Cycles of PLD – 15 Year Data Retention s Single Supply Voltage – 3V (+20%/–10%) s Memory Speed – 100ns Flash memory and SRAM access time for VCC = 3V (+20%/–10%) – 90ns Flash memory and SRAM access time for VCC = 3.3V (+/–10%) Figure 1. 80-lead, Thin, Quad, Flat Package TQFP80 (U) |
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