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PI7C21P100BNH Datasheet(PDF) 11 Page - Pericom Semiconductor Corporation |
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PI7C21P100BNH Datasheet(HTML) 11 Page - Pericom Semiconductor Corporation |
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11 / 79 page  PI7C21P100B 2-PORT PCI-X TO PCI-X BRIDGE Page 11 of 79 November 2005 – Revision 1.02 Name Pin # Type Description P_IRDY# A16 STS Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven HIGH for one cycle. P_TRDY# B15 STS Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven HIGH for one cycle. P_DEVSEL# D21 STS Primary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C21P100B waits for the assertion of this signal within 5 cycles of P_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, it is driven HIGH for one cycle. P_STOP# C4 STS Primary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven HIGH for one cycle. P_LOCK# C14 I Primary LOCK (Active LOW). Asserted by an initiator, one clock cycle after the first address phase of a transaction, attempting to perform an operation that may take more than one PCI transaction to complete. P_IDSEL B19 I Primary ID Select. Used as a chip select line for Type 0 configuration access to PI721P100 configuration space. P_PERR# C8 STS Primary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the primary interface. Before being tri-stated, it is driven HIGH for one cycle. P_SERR# B4 OD Primary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. PI7C21P100B drives this pin on: Address parity error Posted write data parity error on target bus Secondary S_SERR# asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. P_REQ# B21 TS Primary Request (Active LOW): This is asserted by PI7C21P100B to indicate that it wants to start a transaction on the primary bus. PI7C21P100B de-asserts this pin for at least 2 PCI clock cycles before asserting it again. P_GNT# C20 I Primary Grant (Active LOW): When asserted, PI7C21P100B can access the primary bus. During idle and P_GNT# asserted, PI7C21P100B will drive P_AD, P_CBE, and P_PAR to valid logic levels. P_RST# E22 I Primary RESET (Active LOW): When P_RESET# is active, all PCI signals should be asynchronously tri- stated. |
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