SN65LVDS125A

SN65LVDT125A

SLLS595A − OCTOBER 2003 − REVISED FEBRUARY 2004

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8

DE

VOY or VOZ

VOZ or VOY

3 V

1.5 V

0 V

1.4 V

1.25 V

1.2 V

1.2 V

1.15 V

1 V

tPZH

tPHZ

tPZL

tPLZ

Y

Z

1 pF

VOY

VOZ

49.9

Ω ±1%

1.2 V

49.9

Ω ±1%

1 V or 1.4 V

1.2 V

DE

NOTE: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps,

pulse width = 500

± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.

Figure 5. Enable and Disable Time Circuit and Definitions

Clock Input

0 V

VA

VB

1/fo

PRBS Input

0 V

VA

VB

PRBS Output

0 V

VY

VZ

0 V

0 V

0 V

VY − VZ

VY − VZ

VY − VZ

Actual Output

Ideal Output

1/fo

Period Jitter

Cycle-to-Cycle Jitter

Peak-to-Peak Jitter

Actual Output

tjit(pp)

tc(n)

tc(n)

tc(n+1)

tjit(pp) = | tc(n) − 1/fo |

tjit(cc) = |tc(n) −tc(n+1) |

NOTE: A. All input pulses are supplied by an Agilent 81250 Stimulus System.

NOTE: B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software.

Figure 6. Driver Jitter Measurement Waveforms