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IS42S16100 Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc

Part No. IS42S16100
Description  512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
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Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com
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IS42S16100 Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc

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IS42S16100
ISSI®
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/01/01
AC CHARACTERISTICS(1,2,3)
-6
-7
-10
Symbol Parameter
Min.
Max.
Min.
Max.
Min. Max. Units
tCK3
Clock Cycle Time
CAS Latency = 3
6
7
10
ns
tCK2
CAS Latency = 2
8
8.6
10
ns
tAC3
Access Time From CLK(4)
CAS Latency = 3
5.5
6
7
ns
tAC2
CAS Latency = 2
6
6
9
ns
tCHI
CLK HIGH Level Width
2
2.5
3.5
ns
tCL
CLK LOW Level Width
2
2.5
3.5
ns
tOH3
Output Data Hold Time
CAS Latency = 3
2.5
2.5
2.5
ns
tOH2
CAS Latency = 2
2.5
2.5
2.5
ns
tLZ
Output LOW Impedance Time
0
0
0
ns
tHZ3
Output HIGH Impedance Time(5)
CAS Latency = 3
5.5
6
7
ns
tHZ2
CAS Latency = 2
6
6
9
ns
tDS
Input Data Setup Time
2
2
2.5
ns
tDH
Input Data Hold Time
1
1
1
ns
tAS
Address Setup Time
2
2
2.5
ns
tAH
Address Hold Time
1
1
1
ns
tCKS
CKE Setup Time
2
2
2.5
ns
tCKH
CKE Hold Time
1
1
1
ns
tCKA
CKE to CLK Recovery Delay Time
1CLK+3—1CLK+3
—1CLK+3
ns
tCS
Command Setup Time (
CS, RAS, CAS, WE, DQM)
2
2
2.5
ns
tCH
Command Hold Time (
CS, RAS, CAS, WE, DQM)
1
1
1
ns
tRC
Command Period (REF to REF / ACT to ACT)
60
63
70
ns
tRAS
Command Period (ACT to PRE)
42
100,000
42
100,000
50
100,000 ns
tRP
Command Period (PRE to ACT)
18
20
20
ns
tRCD
Active Command To Read / Write Command Delay Time
16
16
20
ns
tRRD
Command Period (ACT [0] to ACT[1])
12
14
20
ns
tDPL3
Input Data To Precharge
CAS Latency = 3
1CLK
1CLK
1CLK
ns
Command Delay time
tDPL2
CAS Latency = 2
1CLK
1CLK
1CLK
ns
tDAL3
Input Data To Active / Refresh
CAS Latency = 3
1CLK+tRP
1CLK+tRP—1CLK+tRP —ns
Command Delay time (During Auto-Precharge)
tDAL2
CAS Latency = 2
1CLK+tRP
1CLK+tRP—1CLK+tRP —ns
tT
Transition Time
1
10
1
10
1
10
ns
tREF
Refresh Cycle Time (4096)
128
128
128 ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated voltages. Also note that the
power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.) when the
output is in the high impedance state.


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