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VIPER50 Datasheet(PDF) 12 Page - STMicroelectronics

Part No. VIPER50
Description  SMPS PRIMARY I.C.
Download  23 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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VIPER50 Datasheet(HTML) 12 Page - STMicroelectronics

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VIPer50/SP - VIPer50A/ASP
OPERATION DESCRIPTION:
CURRENT MODE TOPOLOGY
The current mode control method, like the one
integrated in the VIPer50/50A uses two control
loops - an inner current control loop and an outer
loop
for
voltage
control.
When
the
Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified
output voltage error) the power switch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the power switch and the primary
winding of the transformer.
Excellent D.C. open loop and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation,
instantaneous
correction
to
line
changes and better stability for the voltage
regulation loop.
Current
mode
topology
also
ensures
good
limitation in the case of short circuit. During the
first phase the output current increases slowly
following the dynamic of the regulation loop. Then
it
reaches
the
maximum
limitation
current
internally set and finally stops because the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by limiting the voltage
excursion externally on the COMP pin. An
integrated
blanking
filter
inhibits
the
PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function
prevents
anomalous
or
premature
termination of the switching pulse in the case of
current spikes caused by primary side capacitance
or secondary side rectifier reverse recovery time.
STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary side.
The transition from normal operation to burst
mode operation happens for a power PSTBY given
by:
Where:
LP is the primary inductance of the transformer.
FSW is the normal switching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can be computed as:
tb + td is the sum of the blanking time and of the
propagation time of the internal current sense and
comparator, and roughly represents the minimum
on time of the device. Note that PSTBY may be
affected by the efficiency of the converter at low
load, and must include the power drawn on the
primary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (VCOMP < VCOMPth). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as VDD gets
back to the regulation level and the VCOMPth
threshold is reached, the device operates again.
The
above
cycle
repeats
itself
indefinitely,
providing a burst mode of which the effective duty
cycle is much lower than the minimum one when in
normal
operation.
The
equivalent
switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer50/50A to meet the new German "Blue
Angel" Norm with less than 1W total power
consumption for the system when working in
stand-by. The output voltage remains regulated
around the normal level, with a low frequency
ripple corresponding to the burst mode. The
amplitude of this ripple is low, because of the
output capacitors and because of the low output
current drawn in such conditions. The normal
operation resumes automatically when the power
gets back levels which are higher than PSTBY.
HIGH
VOLTAGE
START-UP
CURRENT
SOURCE
An integrated high voltage current source provides
a bias current from the DRAIN pin during the start-
up phase. This current is partially absorbed by
internal control circuits which are placed into a
standby mode with reduced consumption and are
also provided to the external capacitor connected
to the VDD pin. As soon as the voltage on this pin
reaches the high voltage threshold VDDon of the
P
STBY
1
2
--- L
P
I
2
STBYFSW
=
I
STBY
t
b
t
d
+
()V
IN
L
P
--------------------------------
=


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