 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT89S8253-24PU Datasheet(PDF) 8 Page - ATMEL Corporation |
|
||||||||||||||||||||||||||||||
AT89S8253-24PU Datasheet(HTML) 8 Page - ATMEL Corporation |
|
|
8 / 59 page  8 3286H–MICRO–9/05 AT89S8253 5.1 Auxiliary Register The AUXR Register contains a single active bit called DISALE. 5.2 Clock Register The CLKREG register contains a single active bit called X2. 5.3 SPI Registers Control and status bits for the Serial Peripheral Interface are contained in registers SPCR (see Table 14-1 on page 25) and SPSR (see Table 14-2 on page 26). The SPI data bits are contained in the SPDR register. In normal SPI mode, writing the SPI data register during serial data trans- fer sets the Write Collision bit (WCOL) in the SPSR register. In enhanced SPI mode, the SPDR is also write double-buffered because WCOL works as a Write Buffer Full Flag instead of being a collision flag. The values in SPDR are not changed by Reset. 5.4 Interrupt Registers The global interrupt enable bit and the individual interrupt enable bits are in the IE register. In addition, the individual interrupt enable bit for the SPI is in the SPCR register. Four priorities can be set for each of the six interrupt sources in the IP and IPH registers. IPH bits have the same functions as IP bits, except IPH has higher priority than IP. By using IPH in conjunction with IP, a priority level of 0, 1, 2, or 3 may be set for each interrupt. Table 5-2. AUXR – Auxiliary Register AUXR Address = 8EH Reset Value = XXXX XXX0B Not Bit Addressable – – – – – – Intel_Pwd_Exit DISALE Bit 7 654 32 1 0 Symbol Function DISALE When DISALE = 0, ALE is emitted at a constant rate of 1/6 the oscillator frequency (except during MOVX when 1 ALE pulse is missing). When DISALE = 1, ALE is active only during a MOVX or MOVC instruction. Intel_Pwd_Exit When set, this bit configures the interrupt driven exit from power-down to resume execution on the rising edge of the interrupt signal. When this bit is cleared, the execution resumes after a self-timed interval (nominal 2 ms) referenced from the falling edge of the interrupt signal. Table 5-3. CLKREG – Clock Register CLKREG Address = 8FH Reset Value = XXXX XXX0B Not Bit Addressable ––– –––– X2 Bit 765 43210 Symbol Function X2 When X2 = 0, the oscillator frequency (at XTAL1 pin) is internally divided by 2 before it is used as the device system frequency. When X2 = 1, the divider by 2 is no longer used and the XTAL1 frequency becomes the device system frequency. This enables the user to choose a 6 MHz crystal instead of a 12 MHz crystal, for example, in order to reduce EMI. |
Similar Part No. - AT89S8253-24PU |
|
Similar Description - AT89S8253-24PU |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
