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IDT72T51343L5BB Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72T51343L5BB Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 55 page  10 IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Description Pin No. SI Serial In HSTL-LVTTL modetheserialdatainputisloadedintothefirstdeviceinachain.Whenthatdeviceisloadedandits SENO (L1) INPUT hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice (Continued) connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers. SO Serial Out HSTL-LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain (M3) OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the chain. The SO of the final device in a chain should not be connected. TCK(2) JTAG Clock LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test (A8) INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(2) JTAG Test Data LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan (B9) Input INPUT operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(2) JTAG Test Data LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan (A9) Output OUTPUT operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. TMS(2) JTAG Mode LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the (B8) Select INPUT device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST(2) JTAG Reset LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically (C7) INPUT reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST,thenTRSTcanbetiedwithMRStoensure proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected. WADEN WriteAddress LVTTL The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to (P4) Enable INPUT be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue cycle(s). WADEN should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note, that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part has been completed and SENO has gone LOW. WCLK WriteClock HSTL-LVTTL When enabled by WEN, the rising edge of WCLK writes data into the selected queue via the input bus, (T7) INPUT Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the flag quadrant to be placed on the PAFnbusduringdirectflagoperation.DuringpolledflagoperationthePAFn bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn,PAFand FF outputsareallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXIsignalsarebased on WCLK. The WCLK must be continuous and free-running. WEN WriteEnable HSTL-LVTTL The WEN inputenableswriteoperationstoaselectedqueuebasedonarisingedgeofWCLK.Aqueue (T6) INPUT to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after queue selection provided that WENisLOW.AwriteenableisnotrequiredtocyclethePAFnbus(inpolled mode) or to select the device, (in direct mode). WRADD WriteAddress HSTL-LVTTL For the 8Q device the WRADD bus is 6 bits. The WRADD bus is a dual purpose address bus. The first [5:0] Bus INPUT functionofWRADDistoselectaqueuetobewrittento.Theleastsignificant3bitsofthebus,WRADD[2:0] (WRADD5-T1 are used to address 1 of 8 possible queues within a multi-queue device. The most significant 3 bits, WRADD4-R1 WRADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion WRADD3-R2 mode. These 3 MSb’s will address a device with the matching ID code. The address present on the WRADD2-P3 WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that WRADD1-N1 data present on the Din bus can be written into the previously selected queue on this WCLK edge and WRADD0-N2) on the next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue |
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