 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT723654 Datasheet(PDF) 3 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT723654 Datasheet(HTML) 3 Page - Integrated Device Technology |
|
|
3 / 37 page  3 COMMERCIALTEMPERATURERANGE IDT723654/723664/723674 CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers’ width matches the selected Port B bus width. Each Mailbox register has a flag ( MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on these FIFOs: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for Big- or Little-Endian byte arrangement and selects serial flag programming, parallel flag programming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024. There are two Master Reset pins, MRS1 and MRS2. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset is useful since it permits flushing of the FIFO memory without changing any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1 and PRS2. BothFIFO'shaveRetransmitcapability,whenaRetransmitisperformedon a respective FIFO only the read pointer is reset to the first memory location. A RetransmitisperformedbyusingtheRetransmitMode,RTMpininconjunction with the Retransmit pins RT1 or RT2, for each respective FIFO. Note that the two Retransmit pins RT1 and RT2 are muxed with the Partial Reset pins. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In theFirstWordFallThroughmode(FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/ FWFT pin during Master Reset determines the mode in use. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first long-word (36-bitwide)writtentoanemptyFIFOappearsautomaticallyontheoutputs,no read operation is required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/ FWFTpinduringFIFO operation determines the mode in use. EachFIFOhasacombinedEmpty/OutputReadyFlag( EFA/ORAandEFB/ ORB) and a combined Full/Input Ready Flag ( FFA/IRA and FFB/IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag ( AEA and AEB)anda programmable Almost-Full flag ( AFAandAFB). AEAandAEB indicatewhen aselectednumberofwordsremainintheFIFOmemory. AFAandAFBindicate when the FIFO contains more than a selected number of words. FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are two-stage synchronized to the port clock that reads data from its array. Programmableoffsetsfor AEA,AEB,AFAandAFBareloaded inparallelusing PortAorinserialviatheSDinput.Fivedefaultoffsetsettingsarealsoprovided. The AEA and AEB threshold can be set at 8, 16, 64, 256 or 1,024 locations from the empty boundary and the AFA andAFB thresholdcanbesetat8,16, 64, 256 or 1,024 locations from the full boundary. All these choices are made using the FS0, FS1 and FS2 inputs during Master Reset. Interspersed Parity can also be selected during a Master Reset of the FIFO. If Interspersed Parity is selected then during parallel programming of the flag offset values, the device will ignore data line A8. If Non-Interspersed Parity is selected then data line A8 will become a valid bit. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. The IDT723654/723664/723674 are characterized for operation from 0 °C to 70 °C.Industrialtemperaturerange(-40°Cto+85°C)isavailable.Theyare fabricated using IDT’s high speed, submicron CMOS technology. |
Similar Part No. - IDT723654 |
|
Similar Description - IDT723654 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
