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LM98714 Datasheet(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. LM98714
Description  Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LM98714 Datasheet(HTML) 1 Page - National Semiconductor (TI)

 
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LM98714
Three Channel, 16-Bit, 45 MSPS Digital Copier Analog
Front End with Integrated CCD/CIS Sensor Timing
Generator and LVDS Output
General Description
The LM98714 is a fully integrated, high performance 16-Bit,
45 MSPS signal processing solution for digital color copiers,
scanners, and other image processing applications. High-
speed signal throughput is achieved with an innovative ar-
chitecture utilizing Correlated Double Sampling (CDS), typi-
cally employed with CCD arrays, or Sample and Hold (S/H)
inputs (for Contact Image Sensors and CMOS image sen-
sors). The signal paths utilize 8 bit Programmable Gain
Amplifiers (PGA), a +/-9-Bit offset correction DAC and inde-
pendently controlled Digital Black Level correction loops for
each input. The PGA and offset DAC are programmed inde-
pendently allowing unique values of gain and offset for each
of the three inputs. The signals are then routed to a 45MHz
high performance analog-to-digital converter (ADC). The
fully differential processing channel shows exceptional noise
immunity, having a very low noise floor of -74dB. The 16-bit
ADC has excellent dynamic performance making the
LM98714 transparent in the image reproduction chain.
Applications
n
Multi-Function Peripherals
n
Facsimile Equipment
n
Flatbed or Handheld Color Scanners
n
High-speed Document Scanner
Features
n
LVDS/CMOS Outputs
n
LVDS/CMOS Pixel Rate Input Clock or ADC Input Clock
n
CDS or S/H Processing for CCD or CIS sensors
n
Independent Gain/Offset Correction for Each Channel
n
Digital Black Level Correction Loop for Each Channel
n
Programmable Input Clamp Voltage
n
Flexible CCD/CIS Sensor Timing Generator
Key Specifications
n
Maximum Input Level
1.2 or 2.4 Volt Modes
n
(both with + or - polarity option)
n
ADC Resolution
16-Bit
n
ADC Sampling Rate
45 MSPS
n
INL
+/- 23 LSB (typ)
n
Channel Sampling Rate
15/22.5/30 MSPS
n
PGA Gain Steps
256 Steps
n
PGA Gain Range
0.7 to 7.84x
n
Analog DAC Resolution
+/-9 Bits
n
Analog DAC Range
+/-300mV or +/-600mV
n
Digital DAC Resolution
+/-6 Bits
n
Digital DAC Range
-1024 LSB to + 1008 LSB
n
SNR
-74dB (@0dB PGA Gain)
n
Power Dissipation
505mW (LVDS) 610mW (CMOS)
n
Operating Temp
0 to 70˚C
n
Supply Voltage
3.3V Nominal (3.0V to 3.6V range)
System Block Diagram
20105370
October 2006
© 2006 National Semiconductor Corporation
DS201053
www.national.com


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