Preliminary Technical Data

ADF7021

Rev. PrI | Page 31 of 44

REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER

FS8

0

0

.

1

1

FS7

0

0

.

1

1

FS3

0

0

.

1

1

...

...

...

...

...

...

FS2

0

1

.

1

1

FS1

1

0

.

0

1

CDR_CLK_DIVIDE

1

2

.

254

255

BK2

0

0

1

1

BK1

0

1

0

1

BBOS_CLK_DIVIDE

4

8

16

32

SK8

0

0

.

1

1

SK7

0

0

.

1

1

SK3

0

0

.

1

1

...

...

...

...

...

...

SK2

0

1

.

1

1

SK1

1

0

.

0

1

SEQ_CLK_DIVIDE

1

2

.

254

255

OK2

0

0

...

1

OK1

0

1

...

1

DEMOD_CLK_DIVIDE

INVALID

1

...

15

SEQUENCER CLOCK DIVIDE

AGC CLOCK DIVIDE

CDR CLOCK DIVIDE

DEMOD

CLOCK DIVIDE

ADDRESS

BITS

GD6

0

0

...

1

GD5

0

0

...

1

GD3

0

0

...

1

GD4

0

0

...

1

GD2

0

0

...

1

GD1

0

1

...

1

AGC_CLK_DIVIDE

INVALID

1

...

127

OK3

0

0

...

1

0

0

...

1

OK4

Figure 35.

Register 3—Transmit/Receive Clock Register Comments

•

Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:

DIVIDE

CLK

BBOS

XTAL

CLK

BBOS

_

_

_

=

•

Set the demodulator clock (DEMOD_CLK) such that 2 MHz ≤ DEMOD_CLK ≤ 15 MHz, where:

DIVIDE

CLK

DEMOD

XTAL

CLK

DEMOD

_

_

_

=

•

Data/clock recovery frequency (CDR _CLK) needs to be within 2% of (32 × data rate). The user should choose CDR_CLK frequency

to be as high as possible without breaking this 2% constraint or breaking the DEMOD_CLK condition. This 2% constraint can also

affect the choice of XTAL frequency, depending on the desired data rate.

DIVIDE

CLOCK

CDR

CLK

DEMOD

CLK

CDR

_

_

_

_

=

The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be as close to 100 kHz as possible.

DIVIDE

CLOCK

SEQUENCER

XTAL

CLK

SEQ

_

_

_

=

•

The time allowed for each AGC step to settle is determined by the AGC update rate. It should be set close to 20 kHz.

DIVIDE

AGC

CLK

SEQ

Rate

Update

AGC

_

_

[Hz] =