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ADSP-21020TG-100 Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-21020TG-100 Datasheet(HTML) 2 Page - Analog Devices |
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2 / 32 page  ADSP-21020 REV. C –2– • Instruction Cache The ADSP-21020 includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply- accumulates and FFT butterfly processing. • Hardware Circular Buffers The ADSP-21020 provides hardware to implement circular buffers in memory, which are common in digital filters and Fourier transform implementations. It handles address pointer wraparound, reducing overhead (thereby increasing performance) and simplifying implementation. Circular buffers can start and end at any location. • Flexible Instruction Set The ADSP-21020’s 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21020 can conditionally execute a multiply, an add, a subtract and a branch in a single instruction. DEVELOPMENT SYSTEM The ADSP-21020 is supported with a complete set of software and hardware development tools. The ADSP-21000 Family Development System includes development software, an evaluation board and an in-circuit emulator. • Assembler Creates relocatable, COFF (Common Object File Format) object files from ADSP-21xxx assembly source code. It accepts standard C preprocessor directives for conditional assembly and macro processing. The algebraic syntax of the ADSP-21xxx assembly language facilitates coding and debugging of DSP algorithms. • Linker/Librarian The Linker processes separately assembled object files and library files to create a single executable program. It assigns memory locations to code and to data in accordance with a user-defined architecture file that describes the memory and I/O configuration of the target system. The Librarian allows you to group frequently used object files into a single library file that can be linked with your main program. • Simulator The Simulator performs interactive, instruction-level simulation of ADSP-21xxx code within the hardware configuration described by a system architecture file. It flags illegal operations and supports full symbolic disassembly. It provides an easy-to-use, window oriented, graphical user interface that is identical to the one used by the ADSP-21020 EZ-ICE Emulator. Commands are accessed from pull-down menus with a mouse. • PROM Splitter Formats an executable file into files that can be used with an industry-standard PROM programmer. • C Compiler and Runtime Library The C Compiler complies with ANSI specifications. It takes advantage of the ADSP-21020’s high-level language architec- tural features and incorporates optimizing algorithms to speed up the execution of code. It includes an extensive runtime library with over 100 standard and DSP-specific functions. • C Source Level Debugger A full-featured C source level debugger that works with the simulator or EZ-ICE emulator to allow debugging of assembler source, C source, or mixed assembler and C. • Numerical C Compiler Supports ANSI Standard (X3J11.1) Numerical C as defined by the Numeric C Extensions Group. The compiler accepts C source input containing Numerical C extensions for array selection, vector math operations, complex data types, circular pointers, and variably dimensioned arrays, and outputs ADSP-21xxx assembly language source code. • ADSP-21020 EZ-LAB® Evaluation Board The EZ-LAB Evaluation Board is a general-purpose, stand- alone ADSP-21020 system that includes 32K words of program memory and 32K words of data memory as well as analog I/O. A PC RS-232 download path enables the user to download and run programs directly on the EZ-LAB. In addition, it may be used in conjunction with the EZ-ICE Emulator to provide a powerful software debug environment. • ADSP-21020 EZ-ICE® Emulator This in-circuit emulator provides the system designer with a PC-based development environment that allows nonintrusive access to the ADSP-21020’s internal registers through the processor’s 5-pin JTAG Test Access Port. This use of on-chip emulation circuitry enables reliable, full-speed performance in any target. The emulator uses the same graphical user inter- face as the ADSP-21020 Simulator, allowing an easy tran- sition from software to hardware debug. (See “Target System Requirements for Use of EZ-ICE Emulator” on page 27.) ADDITIONAL INFORMATION This data sheet provides a general overview of ADSP-21020 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-21020 User’s Manual. For development system and programming reference information, refer to the ADSP-21000 Family Development Software Manuals and the ADSP-21020 Programmer’s Quick Reference. Applications code listings and benchmarks for key DSP algorithms are available on the DSP Applications BBS; call (617) 461-4258, 8 data bits, no parity, 1 stop bit, 300/1200/ 2400/9600 baud. ARCHITECTURE OVERVIEW Figure 1 shows a block diagram of the ADSP-21020. The processor features: • Three Computation Units (ALU, Multiplier, and Shifter) with a Shared Data Register File • Two Data Address Generators (DAG 1, DAG 2) • Program Sequencer with Instruction Cache • 32-Bit Timer • Memory Buses and Interface • JTAG Test Access Port and On-Chip Emulation Support Computation Units The ADSP-21020 contains three independent computation units: an ALU, a multiplier with fixed-point accumulator, and a shifter. In order to meet a wide variety of processing needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit floating-point and 40-bit floating-point. The floating-point operations are single-precision IEEE-compatible (IEEE Standard 754/854). The 32-bit floating-point format is EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc. |
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