Electronic Components Datasheet Search |
|
ADSP-21020TG-100 Datasheet(PDF) 5 Page - Analog Devices |
|
ADSP-21020TG-100 Datasheet(HTML) 5 Page - Analog Devices |
5 / 32 page ADSP-21020 REV. C –5– 4 1 × CLOCK CLKIN PMA PMD DMACK DMA DMD ADSP-21010 24 48 32 32 2 PMACK 4 DMPAGE PMPAGE 5 4 ADDR DATA PROGRAM MEMORY SELECTS OE WE PMS1-0 PMRD PMWR DMRD DMWR DMTS DATA MEMORY ACK PERIPHERALS ADDR DATA ADDR DATA SELECTS SELECTS OE WE OE WE RESET IRQ3-0 PMTS DMS3-0 Figure 2. Basic System Configuration The ADSP-21020 also implements on-chip emulation through the JTAG test access port. The processor’s eight sets of break- point range registers enable program execution at full speed until reaching a desired break-point address range. The processor can then halt and allow reading/writing of all the processor’s internal registers and external memories through the JTAG port. PIN DESCRIPTIONS This section describes the pins of the ADSP-21020. When groups of pins are identified with subscripts, e.g. PMD47–0, the highest numbered pin is the MSB (in this case, PMD47). Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI, and TRST). Those that are asynchronous (A) can be asserted asynchronously to CLKIN. O = Output; I = Input; S = Synchronous; A = Asynchronous; P = Power Supply; G = Ground. Pin Name Type Function PMA23–0 O Program Memory Address. The ADSP-21020 outputs an address in program memory on these pins. PMD47–0 I/O Program Memory Data. The ADSP-21020 inputs and outputs data and instructions on these pins. 32-bit fixed-point data and 32-bit single-precision floating-point data is trans- ferred over bits 47-16 of the PMD bus. PMS1–0 O Program Memory Select lines. These pins are asserted as chip selects for the corresponding banks of program memory. Memory banks must be defined in the memory control registers. These pins are decoded program memory address lines and provide an early indication of a possible bus cycle. PMRD O Program Memory Read strobe. This pin is asserted when the ADSP-21020 reads from program memory. PMWR O Program Memory Write strobe. This pin is asserted when the ADSP-21020 writes to program memory. PMACK I/S Program Memory Acknowledge. An external device deasserts this input to add wait states to a memory access. Pin Name Type Function PMPAGE O Program Memory Page Boundary. The ADSP-21020 asserts this pin to signal that a program memory page boundary has been crossed. Memory pages must be defined in the memory control registers. PMTS I/S Program Memory Three-State Control. PMTS places the program memory address, data, selects, and strobes in a high- impedance state. If PMTS is asserted while a PM access is occurring, the processor will halt and the memory access will not be completed. PMACK must be asserted for at least one cycle when PMTS is deasserted to allow any pending memory access to com- plete properly. PMTS should only be asserted (low) during an active memory access cycle. DMA31–0 O Data Memory Address. The ADSP-21020 outputs an address in data memory on these pins. DMD39–0 I/O Data Memory Data. The ADSP-21020 inputs and outputs data on these pins. 32-bit fixed point data and 32-bit single-precision floating point data is transferred over bits 39-8 of the DMD bus. DMS3–0 O Data Memory Select lines. These pins are asserted as chip selects for the correspon- ding banks of data memory. Memory banks must be defined in the memory control registers. These pins are decoded data memory address lines and provide an early indication of a possible bus cycle. DMRD O Data Memory Read strobe. This pin is asserted when the ADSP-21020 reads from data memory. DMWR O Data Memory Write strobe. This pin is asserted when the ADSP-21020 writes to data memory. DMACK I/S Data Memory Acknowledge. An external device deasserts this input to add wait states to a memory access. |
Similar Part No. - ADSP-21020TG-100 |
|
Similar Description - ADSP-21020TG-100 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |