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ABSOLUTE MAXIMUM RATINGS

bq24730

SLUS695 – MARCH 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

DESCRIPTION

NO.

NAME

Battery to system switch driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the

system from the battery to prevent current flow from the system to the battery, while allowing a low impedance path

from battery to system and while discharging the battery pack to the system load. Connect this pin directly to the gate

of the input BAT PMOS power FET. Connect the source of the FET to the system load voltage node. Connect the

31

BATDRV

drain of the FET to the battery pack positive node. Placing a 10-k

Ω resistor from the gate to the source of the BAT

FET to keep the FET off when there is no power to the IC is recommended. An optional capacitor is placed from the

gate to the source to slow-down the switching times. The internal gate drive is asymmetrical allowing a quick turn-off

and slower turn-off in addition to the internal break-before-make logic with respect to the ACDRV.

Battery pack cell select logic input. Logic low (LO) input programs 3-cell Li-Ion output voltage (12.6 V). Logic high (HI)

32

CELLS

input programs 4-cell Li-Ion output voltage (16.8 V)

Charger status, open-drain output. Logic low(LO) output indicates charger is on. Logic high (HI) output indicates

33

STAT

controller is not charging. A 10-k

Ω pull-up resistor to the host controller supply rail is needed.

Power ground. Ground connection for the high-current power converter nodes. Only connect to the AGND and GND

34

PGND

nodes by connecting to the PowerPAD™ underneath the IC.

35

LODRV

PWM low side driver output. Connect directly to the gate of the low-side NMOS power FET with a short trace.

Low-side driver gate voltage regulator and source for high-side driver bootstrap voltage. Add a 1-

µF ceramic capacitor

36

REGN

from REGN pin to PGND pin, close to the IC. Place a small signal Schottky diode from REGN to BTST for bootstrap

voltage.

Synchronous buck phase node. Connect directly to the source of the high-side NMOS FET with a short trace. This

37

PH

node is the common connection between the high-side FET, low-side FET, and output inductor. Connect a 0.1-

µF

boot-strap ceramic capacitor from BTST to PH.

38

HIDRV

PWM high side driver output. Connect directly to the gate of the high-side NMOS power FET with a short trace.

High-side FET Boot-strap input pin. Connect to positive side of boot-strap capacitor. Connect a 0.1-

µF bootstrap

capacitor from the BTST pin to the PH node. Also, connect a bootstrap diode with the anode connected to the REGN

39

BTST

pin and the cathode connected to the BTST pin. An optional 4.7-

Ω - 15-Ω series resistor is placed between the BTST

pin and the bootstrap-diode/capacitor junction to slow-down the turn-on time of the high-side FET for reducing ringing

due to high dv/dt of the phase node.

IC power positive supply. Connect directly to the drain of the high-side NMOS power FET. A 0.1-

µF decoupling

40

PVCC

ceramic capacitor is recommended from PVCC to PGND.

PIN

VALUE / UNIT

ACN, ACP, PVCC, ACDRV, SYNN, SYNP, SRP, SRN , BATDRV,

–0.3 V to 30 V

BAT, BYPASS, SYS, VCC

PH

–1 V to 30 V

Supply voltage range

LODRV, REGN, FBO, EAI, EAO, ACGOOD, ISYNSET, CHGEN,

VREF5, ACDET, IBAT, STAT, ACSET, AIRDET, DPMDET,

–0.3 V to 7 V

LBSET, IADSLP, LOWBAT, IADAPT, SRSET, CELLS

BTST, HIDRV (with respect to AGND and PGND)

–1 V to 36 V

Maximum differential voltage

AGND-PGND, AGND-DGND

–0.3 V to 0.3 V

Maximum difference voltage

ACP–ACN , SRP–SRN, and SYNP–SYNN

0.6 V

–40

°C to 85°C

150

°C

–65

°C to 150°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are with respect to AGND, unless otherwise noted. Currents are positive into, negative out of the specified terminal. Consult

Packaging Section of the Data book for thermal limitations and considerations of packages.

4

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