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PS4066ACEE Datasheet(PDF) 5 Page - Pericom Semiconductor Corporation |
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PS4066ACEE Datasheet(HTML) 5 Page - Pericom Semiconductor Corporation |
5 / 9 page 5 PS8184A 10/15/98 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Electrical Specifications - Single +3V Supply (V+ = +2.7V to 3.3V, GND = 0V, V INH = 2.4V, VINL = 0.8V) r e t e m a r a Pl o b m y Ss n o it i d n o CC ° p m e T. n i M ) 1 ( p y T ) 2 ( . x a M ) 1 ( s ti n U h c ti w S g o l a n A e g n a R l a n g i S g o l a n A ) 3 ( V G O L A N A 0+ VV e c n a t si s e R - n O l e n n a h CR N O I , V 3 = + V M O C , A m 1 - = V O N V 5 . 1 = 5 20 7 1 Ω ll u F5 2 2 c i m a n y D e m i T - n O - n r u T ) 3 ( t N O V , V 3 = + V O N V 5 . 1 = 5 20 85 8 1 s n ll u F0 3 2 e m i T -f f O - n r u T ) 3 ( t ) F F O ( V , V 3 = + V O N V 5 . 1 = 5 20 40 5 1 ll u F0 0 2 n o it c e j n I e g r a h C ) 3 ( Q CL V , F n 1 = N E G , V 0 = R N E G V 0 = 5 22 0 1C p y l p p u S t n e rr u C y l p p u S e v it i s o P+ I V , V 3 . 3 = + V N I , + V r o V 0 = ff o r o n o sl e n n a h c ll a ll u F1 -1 0 0 . 01 µA Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design 4. ∆RΟΝ = ∆RΟΝ max - ∆RΟΝ min 5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured. 6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25ºC. 7. Off Isolation = 20log10 [ VCOM / (VNO or VNO) ], VCOM = 0utput, VNC /VNO = input to off switch 8. Between any two switches. |
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