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PRELIMINARY
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Document Number: 38-05616 Rev. **
Page 3 of 24
2M x 18 Array
Write
Reg
Write
Reg
Logic Block Diagram (CY7C1418AV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS[1:0]
VREF
18
21
C
C
18
LD
Control
Burst
Logic
A0
A(20:1)
20
CQ
CQ
R/W
DOFF
Logic Block Diagram (CY7C1420AV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS[3:0]
VREF
36
20
C
C
36
LD
Control
Burst
Logic
A0
A(19:1)
19
1M x 36 Array
Write
Reg
Write
Reg
CQ
CQ
36
R/W
DOFF
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