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IDT72T51256L5BBI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72T51256L5BBI Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 62 page  7 IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIALANDINDUSTRIAL TEMPERATURERANGES BM BusMatching LVTTL This pin is setup before Master Reset and must not toggle during any device operation. This pin is used (L14) INPUT along with IW and OW to setup the multi-queue flow-control device bus width. Please refer to Table 3 fordetails. D[35:0] Data Input Bus HSTL-LVTTL These are the 36 data input pins. Data is written into the device via these input pins on the rising edge Din INPUT of WCLK provided that WEN is LOW. Note, that in Packet mode D32-D35 may be used as packet (See Pin No. markers,pleaseseepacketreadyfunctionaldiscussionformoredetail.Duetobusmatchingnotallinputs table for details) may be used, any unused inputs should be tied LOW. DF(1) Default Flag LVTTL If the user requires default programming of the multi-queue device, this pin must be setup before Master (L3) INPUT Reset and must not toggle during any device operation. The state of this input at master reset determines the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128. DFM(1) Default Mode LVTTL The multi-queue device requires programming after master reset. The user can do this serially via the (L2) INPUT serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be selected, if HIGH then default mode is selected. ERCLK RCLK Echo HSTL-LVTTL ReadClockEchooutput,thisoutputgeneratesaclockbasedonthereadclockinput,thisisusedforSource (R10) OUTPUT SynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfromthequeue. EREN REN Echo HSTL-LVTTL Read Enable Echo output, can be used in conjunction with the ERCLK output to load data output from the (R11) OUTPUT queue into the receiving device. ESTR PAEn Flag Bus LVTTL If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK (R15) Strobe INPUT and the RDADD bus to select a device for its queues to be placed on to the PAEn bus outputs. A device addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted and SENO has gone LOW. ESYNC PAEn Bus Sync HSTL-LVTTL ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus (R16) OUTPUT during Polled operation of the PAEn bus. During Polled operation each device's queue status flags are loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads device 1 onto PAEn, the second RCLK rising edge loads device 2 and so on. During the RCLK cycle that a selected device is placed on to the PAEn bus, the ESYNC output will be HIGH. EXI PAEnBus LVTTL The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn (T16) Expansion In INPUT bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The EXI receives a token from the previous device in a chain. In single device mode the EXI input must be tied LOW if the PAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput must be connected to the EXO output of the same device. In expansion mode the EXI of the first device should be tied LOW, when direct mode is selected. EXO PAEnBus LVTTL EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled (T15) Expansion Out OUTPUT PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This pin pulses when device N places its PAE status on to the PAEn/PRn bus with respect to RCLK. This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising edge the first quadrant of device N+1 will be loaded on to the PAEnbus.Thiscontinuesthroughthechainand EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device in the chain provides synchronization to the user of this looping event. FF Full Flag HSTL-LVTTL This pin provides the full flag output for the active queue, that is, the queue selected on the input port (P8) OUTPUT for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue selection, this flag will show the status of the newly selected queue. Data can be written to this queue on the next cycle provided FFisHIGH.ThisflaghasHigh-Impedancecapability,thisisimportantduring expansionofdevices,whenthe FFflagoutputofupto8devicesmaybeconnectedtogetheronacommon line. The device with a queue selected takes control of the FFbus,allotherdevicesplacetheirFFoutput into High-Impedance. When a queue selection is made on the write port this output will switch from High- Impedance control on the next WCLK cycle. This flag is synchronized to WCLK. PIN DESCRIPTIONS Symbol & Name I/O TYPE Description Pin No. |
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