NB3N2304NZ

http://onsemi.com

2

Figure 2. Block Diagram

Figure 3. NB3N2304NZ Package Pinout (Top View)

Q1

Q2

Q3

Q4

IN

Logic

Control

OE

1

2

3

4

8

7

6

5

Q4

Q3

Q2

IN

OE

Q1

GND

Table 1. PIN DESCRIPTION

Pin #

Pin

Name

Type

Description

1

IN

LVCMOS/LVTTL Input

Clock Input

2

OE

LVCMOS/LVTTL Input

Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs

are forced to logic LOW when OE is forced LOW.

3

Q1

LVCMOS/LVTTL Output

Clock Output 1

4

GND

Power

Negative Supply Voltage; Connect to Ground, 0 V

5

Q2

(LV)CMOS/(LV)TTL Input

Clock Output 2

6

Power

Positive Supply Voltage (3.0 V to 3.6 V)

7

Q3

(LV)CMOS/(LV)TTL Output

Clock Output 3

8

Q4

(LV)CMOS/(LV)TTL Input

Clock Output 4

Table 2. OE, OUTPUT ENABLE FUNCTION TABLE

Inputs

Outputs

IN

OE

L

L

L

H

L

L

L

H

L

H

H

H