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ISL6264 Datasheet(PDF) 22 Page - Intersil Corporation |
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ISL6264 Datasheet(HTML) 22 Page - Intersil Corporation |
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22 / 24 page  22 FN6359.1 October 16, 2006 Dynamic Mode of Operation - Dynamic Droop using DCR sensing Droop is very important for load transient performance. If the system is not compensated correctly, the output voltage could sag excessively upon load application and potentially create a system failure. The output voltage could also take a long period of time to settle to its final value. This could be problematic if a load dump were to occur during this time. This situation would cause the output voltage to rise above the no load setpoint of the converter and could potentially damage the CPU. The L/DCR time constant of the inductor must be matched to the Rn*Cn time constant as shown in Equation 18: Solving for Cn, we now have Equation 19: Note, RO was neglected. As long as the inductor time constant matches the Cn, Rn and RS time constants as given above, the transient performance will be optimum. As in the Static Droop Case, this process may require a slight adjustment to correct for layout inconsistencies. For the example of L = 0.36 H with 0.8m Ω DCR, C n is calculated below. The value of this capacitor is selected to be 330nF. As the inductors tend to have 20% to 30% tolerances, this cap generally will be tuned on the board by examining the transient voltage. If the output voltage transient has an initial dip (lower than the voltage required by the load line) and slowly increases back to the steady state, the cap is too small and vice versa. It is better to have the cap value a little bigger to cover the tolerance of the inductor to prevent the output voltage from going lower than the spec. This cap needs to be a high grade cap like X7R with low tolerance. There is another consideration in order to achieve better time constant match mentioned above. The NPO/COG (class-I) capacitors have only 5% tolerance and a very good thermal characteristics. But those caps are only available in small capacitance values. In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier has to be resized up to 10X to reduce the capacitance by 10X. But attention has to be paid in balancing the impedance of droop amplifier in this case. Dynamic Mode of Operation - Compensation Parameters Considering the voltage regulator as a black box with a voltage source controlled by VID and a series impedance, in order to achieve the 2.0mV/A load line, the impedance needs to be 2.0m Ω. The compensation design has to target the output impedance of the converter to be 2.0m Ω. There is a mathematical calculation file available to the user. The power stage parameters such as L and Cs are needed as the input to calculate the compensation component values. Attention has to be paid to the input resistor to the FB pin. It is better to keep this resistor at 1k Ω for the convenience of OFFSET design. Static Mode of Operation - Current Balance using DCR or Discrete Resistor Current Sensing Current Balance is achieved in the ISL6264 through the matching of the voltages present on the ISEN pins. The ISL6264 adjusts the duty cycles of each phase to maintain equal potentials on the ISEN pins. RL and CL around each inductor, or around each discrete current resistor, are used to create a rather large time constant such that the ISEN voltages have minimal ripple voltage and represent the DC current flowing through each channel's inductor. For optimum performance, RL is chosen to be 10k Ω and CL is selected to be 0.22µF. When discrete resistor sensing is used, a capacitor most likely needs to be placed in parallel with RL to properly compensate the current balance circuit. ISL6264 uses RC filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. Even though the ISL6264 forces the ISEN voltages to be almost equal, the inductor currents will not be exactly equal. Take DCR current sensing as example, two errors have to be added to find the total current imbalance. 1) Mismatch of DCR: If the DCR has a 5% tolerance then the resistors could mismatch by 10% worst case. If each phase is carrying 20A then the phase currents mismatch by 20A*10% = 2A. 2) Mismatch of phase voltages/offset voltage of ISEN pins. The phase voltages are within 2mV of each other by current balance circuit. The error current that results is given by 2mV/DCR. If DCR = 1m Ω then the error is 2A. 2.05 2.1 2.15 2.2 2.25 020 40 60 80 INDUCTOR TEMPERATURE (°C) 100 FIGURE 33. LOAD LINE PERFORMANCE WITH NTC THERMAL COMPENSATION L DCR ------------- R n RSEQV ⋅ R n RS EQV + ---------------------------------- C n ⋅ = (EQ. 18) C n L DCR ------------- R n RSEQV ⋅ R n RS EQV + ---------------------------------- ----------------------------------- = (EQ. 19) C n 0.36 µH 0.0008 -------------------- parallel 5.823k, 1.825k () ------------------------------------------------------------------- 330nF == (EQ. 20) ISL6264 |
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