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ISL6264 Datasheet(PDF) 6 Page - Intersil Corporation

Part No. ISL6264
Description  Two-Phase Core Controller for AMD Mobile Turion CPUs
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6264 Datasheet(HTML) 6 Page - Intersil Corporation

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6
FN6359.1
October 16, 2006
Functional Pin Description
SET
Logic low enables the audio filter which only allows above
20kHz operation. Logic high disables the audio filter.
RBIAS
147k resistor to GND sets internal current reference, ~10µA,
for the overcurrent protection setting.
OFS
A resistor from this pin to GND programs a DC current
source for generating a positive offset voltage across the
resistor between FB and VDIFF pins. The OFS pin voltage is
1.2V.
SOFT
A capacitor from this pin to GND pin sets the maximum slew
rate of the output voltage. The SOFT pin is the non-inverting
input of the error amplifier. A 210µA internal current source is
generated to charge or discharge the SOFT pin capacitor to
determine the slew-rate of VID. During the start-up process,
the current source is reduced to 43µA.
OCSET
Overcurrent protection set input. A resistor from this pin to
VO sets DROOP voltage limit for OC trip. A 10µA current
source is connected internally to this pin.
VW
A resistor from this pin to COMP programs the switching
frequency (for example, 6.81k ~ 300kHz).
COMP
This pin is the output of the error amplifier.
FB
This pin is the inverting input of the error amplifier.
VDIFF
This pin is the output of the differential amplifier.
VSEN
Remote core voltage sense input.
RTN
Remote core voltage sense return.
DROOP
Output of the droop amplifier. The voltage level at this pin is
the sum of Vo and the programmed droop voltage by the
external resistors.
DFB
This pin is the inverting input of the droop amplifier.
VO
An input to IC reporting the local output voltage.
VSUM
This pin is connected to the summation junction of channel
current sensing.
VIN
It is used for input voltage feed forward to improve input line
transient performance.
GND
Signal ground. Connect to local controller ground.
VCC
5V bias power supply for the ISL6264 controller.
ISEN2
Individual current sharing sensing for channel 2.
ISEN1
Individual current sharing sensing for channel 1.
BOOT2
This pin is the upper gate driver supply voltage for phase 2.
An internal boot strap diode is connected to the PVCC pin.
UGATE2
Upper MOSFET gate signal for phase 2.
PHASE2
The phase node of phase 2. This pin should connect to the
source of upper MOSFET. It is the return path for the upper
MOSFET drive.
PGND2
The return path of the lower gate driver for phase 2.
LGATE2
Lower-side MOSFET gate signal for phase 2.
1
40
2
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9
10
30
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39
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37
36
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11
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UGATE1
PHASE1
PGND1
LGATE1
PVCC
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
SET
RBIAS
OFS
SOFT
OCSET
VW
COMP
FB
VDIFF
VSEN
GND PAD
(BOTTOM)
ISL6264


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