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MC3S12HZ256J3MAL Datasheet(PDF) 100 Page - Freescale Semiconductor, Inc |
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MC3S12HZ256J3MAL Datasheet(HTML) 100 Page - Freescale Semiconductor, Inc |
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100 / 692 page  Chapter 3 2 Kbyte EEPROM Module (EETS2KV1) MC9S12HZ256 Data Sheet, Rev. 2.04 100 Freescale Semiconductor All bits in the ECLKDIV register are readable while bits 6-0 are write once and bit 7 is not writable. 3.3.2.2 RESERVED1 This register is reserved for factory testing and is not accessible to the user. All bits read 0 and are not writable. 3.3.2.3 RESERVED2 This register is reserved for factory testing and is not accessible to the user. 76543210 R EDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 3-4. EEPROM Clock Divider Register (ECLKDIV) Table 3-3. ECLKDIV Field Descriptions Field Description 7 EDIVLD Clock Divider Loaded 0 Register has not been written. 1 Register has been written to since the last reset. 6 PRDIV8 Enable Prescaler by 8 0 The oscillator clock is directly fed into the ECLKDIV divider. 1 The oscillator clock is divided by 8 before feeding into the clock divider. 5:0 EDIV[5:0] Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to Section 3.4.1.1, “Writing the ECLKDIV Register” for more information. 76543210 R 00000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 3-5. RESERVED1 76543210 R 00000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 3-6. RESERVED2 |
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